Digitally programmable analog duty-cycle correction circuit

A system for digitally controlling an analog duty-cycle correction circuit, comprising:

• a transmitter configured to generate output based on a clock associated with the analog duty-cycle correction circuit;
• a duty-cycle distortion detector circuit configured to facilitate digital control of a duty-cycle of the clock associated with the analog duty-cycle correction circuit based on a duty-cycle distortion error associated with the output of the transmitter;
• an accumulator component configured to receive and accumulate bits of data that are representative of the duty-cycle distortion error, and convert the bits of data to a multiple-bit duty-cycle distortion error code word that is indicative of the duty-cycle distortion error;
• a core component configured to receive a first input data stream having a first defined data pattern, a second input data stream having a second defined data pattern, a first clock signal associated with the clock, and a second clock signal associated with the clock, wherein the output comprises a first output data stream and a second output data stream generated based on the first input data stream, the second input data stream, the first clock signal, and the second clock signal, the duty-cycle distortion detector circuit is configured to determine a first average value of the first output data stream and a second average value of the second output data stream, determine a differential average value of the first average value and the second average value, and determine the duty-cycle distortion error, based on the differential average value,
• wherein the bits of data comprise the differential average value, wherein the multiple-bit duty-cycle distortion error code word is generated based on the differential average value, and
• wherein an offset value is determined based on the multiple-bit duty-cycle distortion error code word associated with the duty-cycle distortion error, and wherein a bias current corresponding to the offset value is generated, based on the multiple-bit duty-cycle distortion error code word, and is applied to drains of transistors of an amplifier of the analog duty-cycle correction circuit to control the analog duty-cycle correction circuit to modify the first clock signal and the second clock signal, based on the offset value, to mitigate the duty-cycle distortion error;
• a set of switches associated with a gate of a transistor;
• and
• a current source device configured to facilitate applying the offset signal to the amplifier of the analog duty-cycle correction circuit:
• at a first time, control a switch of the set of switches to place the switch in a first state to provide a bias voltage to the gate of the transistor to switch the transistor to an on state;
• and
• at a second time, control the switch to place the switch in a second state to discontinue providing the bias voltage to the gate of the transistor to switch the transistor to an off state.

A method, comprising:

• generating output, comprising a first output data signal and a second output data signal, of a transmitter, based on a first input data signal having a first defined input data bit pattern, a second input data signal having a second defined input data bit pattern, and a first clock signal and a second clock signal associated with a clock associated with an analog duty-cycle correction circuit;
• determining a first average value of the first output data signal and a second average value of the second output data signal;
• determining a differential average value of the first average value and the second average value based on comparing the first average value to the second average value;
• determining a duty-cycle distortion error associated with the output of the transmitter based on the differential average value;
• accumulating bits of data that are indicative of the duty-cycle distortion error, wherein the bits of data comprise the differential average value;
• generating a digital multiple-bit duty-cycle distortion error code word associated with the duty-cycle distortion error based on the differential average value;
• based on the digital multiple-bit duty-cycle distortion error code word associated with the duty-cycle distortion error, generating an offset signal comprising a bias current corresponding to an offset value that is applied to drains of transistors of an amplifier of the analog duty-cycle correction circuit to control a duty-cycle of the clock associated with the analog duty-cycle correction circuit to control the first clock signal and the second clock signal;
• associating a set of switches with a gate of a transistor;
• and
• to facilitate applying the offset signal to the amplifier of the analog duty-cycle correction circuit:
• at a first time, controlling a switch of the set of switches to place the switch in a first state to provide a bias voltage to the gate of the transistor to switch the transistor to an on state;
• and
• at a second time, controlling the switch to place the switch in a second state to discontinue providing the bias voltage to the gate of the transistor to switch the transistor to an off state.