Electrostatic prevention circuit, array substrate and display device

An electrostatic prevention circuit, comprising:

• a first thin film transistor and a first capacitor, wherein,
• a gate electrode of the first thin film transistor is connected to a first electrode of the first capacitor;
• the electrostatic prevention circuit further comprises a second thin film transistor, a third thin film transistor, a fourth thin film transistor, and a second capacitor;
• a second electrode of the first capacitor is connected to a first electrode of the first thin film transistor, a first electrode of the second thin film transistor and a second electrode of the fourth thin film transistor;
• a gate electrode of the third thin film transistor is connected to a first electrode of the second capacitor, and a second electrode of the second capacitor is connected to a first electrode of the third thin film transistor, a first electrode of the fourth thin film transistor and a second electrode of the second thin film transistor;
• a gate electrode of the second thin film transistor is connected to a second electrode of the first thin film transistor;
• and
• a gate electrode of the fourth thin film transistor is connected to a second electrode of the third thin film transistor.