Multi-layer structure to increase crystalline temperature of a selector device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorHai-Dang Trinh
Life of this patent
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Abstract
In some embodiments, a semiconductor device is provided. The semiconductor device includes a first amorphous switching structure disposed over a first electrode. A buffer structure is disposed over the first amorphous switching structure. A second amorphous switching structure is disposed over the buffer structure. A second electrode is disposed over the second amorphous switching structure, where the first and second amorphous switching structures are configured to switch between low resistance states and high resistance states depending on whether a voltage from the first electrode to the second electrode exceeds a threshold voltage.
Claims20
An integrated chip, comprising:
- a selector-memory cell stack disposed between a first conductive line and a second conductive line, wherein the selector-memory cell stack comprises:
- a memory cell electrically coupled to and disposed between the second conductive line and an electrode;
- and
- a threshold selector electrically coupled to and disposed between the first conductive line and the electrode, wherein the threshold selector comprises a plurality of amorphous switching structures and a plurality of buffer structures, wherein the buffer structures and the amorphous switching structures are alternatingly stacked between the electrode and the first conductive line, wherein there are more of the buffer structures than the amorphous switching structures disposed between the electrode and the first conductive line, and wherein the buffer structures are amorphous solids.
An integrated chip, comprising:
- a selector device electrically coupled to a memory cell, wherein the selector device comprises:
- a plurality of amorphous switching structures disposed between a first electrode and a second electrode, wherein the amorphous switching structures are chalcogenides, and wherein the amorphous switching structures are configured to switch between low resistance states and high resistance states based on a voltage between the first electrode and the second electrode;
- and
- a plurality of buffer structures disposed between the first electrode and the second electrode, wherein the buffer structures and the amorphous switching structures are alternatingly stacked between the first electrode and the second electrode, and wherein there are more of the buffer structures than the amorphous switching structures disposed between the first electrode and the second electrode.
A method for forming a semiconductor device, the method comprising:
- forming a first conductive layer over a semiconductor substrate;
- forming a first amorphous switching layer over the first conductive layer;
- forming a buffer layer over the first amorphous switching layer;
- forming a second amorphous switching layer over the buffer layer;
- etching the first conductive layer, the first amorphous switching layer, the buffer layer, and the second amorphous switching layer to form a first conductive line, a first amorphous switching structure, a buffer structure, and a second amorphous switching structure, respectively;
- forming a dielectric layer over the semiconductor substrate and laterally surrounding the first amorphous switching structure, the buffer structure, and the second amorphous switching structure;
- and
- forming a conductive wire over the second amorphous switching structure and the dielectric layer, wherein forming the conductive wire comprises heating the semiconductor substrate to a fabrication temperature greater than about 400° C., and wherein the first amorphous switching structure and the second amorphous switching structure remain amorphous solids above the fabrication temperature.
Dependencies are inferred from the claim text.