Fin field effect transistor (finFET) device structure and method for forming the same

A fin field effect transistor (FinFET) device structure, comprising:

• a first fin structure having first sidewalls and a third fin structure having third sidewalls over a first region of a substrate;
• a second fin structure having second sidewalls and a fourth fin structure having fourth sidewalls over a second region of the substrate;
• a first isolation structure over the first region, wherein the first fin structure and the third fin structure are protruded from a first top surface of the first isolation structure;
• a second isolation structure over the second region, wherein the second fin structure and the fourth fin structure are protruded from a second top surface of the second isolation structure, and
• wherein a first angle is between one of the first sidewalls of the first fin structure and the first top surface of the first isolation structure, a second angle is between one of the second sidewalls of the second fin structure and the second top surface of the second isolation structure, and the first angle is smaller than the second angle, and the first top surface of the first isolation structure is higher than the second top surface of the second isolation structure, and
• wherein the first fin structure and the third fin structure have a constant fin width from a bottom portion to a top portion between the first sidewalls and the third sidewalls respectively, and the constant fin width of the first fin structure and the third fin structure is smaller than a width of the second fin structure and the fourth fin structure at the second top surface of the second isolation structure;
• and
• a gate dielectric layer over the first fin structure, the second fin structure, the third fin structure, the fourth fin structure, the first isolation structure and the second isolation structure, wherein
• a first distance between a top portion of the gate dielectric layer on one of the first sidewalls of the first fin structure and a top portion of the gate dielectric layer on one of the third sidewalls of the third fin structure is smaller than a second distance between a top portion of the gate dielectric layer on one of the second sidewalls of the second fin structure and a top portion of the gate dielectric layer on one of the fourth sidewalls of the fourth fin structure,
• wherein the top portion of the gate dielectric layer on one of the first sidewalls of the first fin structure faces the top portion of the gate dielectric layer on one of the third sidewalls of the third fin structure, and the top portion of the gate dielectric layer on one of the second sidewalls of the second fin structure faces the top portion of the gate dielectric layer on one of the fourth sidewalls of the fourth fin structure.

A fin field effect transistor (FinFET) device structure, comprising:

• a first isolation structure over a substrate;
• a second isolation structure over the substrate;
• a first fin structure and a third fin structure having vertical sidewall surfaces extending through and protruding from a first top surface of the first isolation structure, wherein the first fin structure and the third fin structure have a constant fin width from a bottom portion to a top portion, the first fin structure has a first fin height measured from a first top surface of the first fin structure to the first top surface of the first isolation structure;
• a second fin structure and a fourth fin structure having sloped sidewall surfaces extending through and protruding from a second top surface of the second isolation structure, wherein the second fin structure and the fourth fin structure have a tapered fin width which is tapered from a bottom portion to a top portion, and the second fin structure has a second fin height measured from a second top surface of the second fin structure to the second top surface of the second isolation structure, and the first fin height is smaller than the second fin height, and
• wherein the constant fin width of the first fin structure and the third fin structure is smaller than the tapered fin width of the second fin structure and the fourth fin structure;
• and
• a gate dielectric layer over the first fin structure, the second fin structure, the third fin structure, the fourth fin structure, the first isolation structure and the second isolation structure, wherein
• a first pitch between the vertical sidewall surface of the first fin structure and the third fin structure is smaller than a second pitch between the sloped sidewall surface of the second fin structure and the fourth fin structure, and the first top surface of the first isolation structure between the vertical sidewall surface of the first fin structure and the third fin structure is higher than the second top surface of the second isolation structure between the sloped sidewall surface of the second fin structure and the fourth fin structure.