Methods of manufacturing low-temperature polysilicon thin film and transistor

A method of manufacturing a low temperature polysilicon thin film, comprising:

• forming a buffer layer on a substrate;
• forming a gate electrode on the buffer layer;
• forming a patterned raising layer on the gate electrode, wherein the patterned raising layer covers a top surface and a lateral surface of the gate electrode;
• forming a first diffusion barrier layer on the patterned raising layer;
• forming a second diffusion barrier layer on the first diffusion barrier layer;
• forming a silicon layer on the second diffusion barrier layer;
• forming an impurity collection layer on the silicon layer, wherein the impurity collection layer has pores for impurities diffusing from the substrate;
• keeping the impurity collection layer on the silicon layer and annealing by laser beam irradiating the silicon layer to form a polysilicon layer, wherein the polysilicon layer includes a patterned area and a to-be-removed area, the patterned area has the same pattern with the patterned raising layer, and the patterned area is whole directly above the patterned raising layer;
• and
• in the polysilicon layer, removing the to-be-removed area, and keeping the patterned area.

A method of manufacturing a low temperature polysilicon thin film transistor, comprising the steps of:

• forming a buffer layer on a substrate;
• forming a gate electrode on the buffer layer;
• forming a patterned raising layer on the gate electrode, wherein the patterned raising layer covers a top surface and a lateral surface of the gate electrode;
• forming a first diffusion barrier layer on the patterned raising layer;
• forming a second diffusion barrier layer on the first diffusion barrier layer;
• forming a silicon layer on the second diffusion barrier layer;
• annealing the silicon layer to form a polysilicon layer, wherein the polysilicon layer includes a patterned area and a to-be-removed area, the patterned area has the same pattern with the patterned raising layer, and the patterned area is whole directly above the patterned raising layer;
• in the polysilicon layer, removing the to-be-removed area, and keeping the patterned area;
• and
• forming a source electrode and a drain electrode, wherein the source electrode and the drain electrode are electrically connected to the polysilicon layer.