Vertical field effect transistor device having protruded shallow trench isolation and method for manufacturing the same

A method for manufacturing a vertical field effect transistor (VFET) device, the method comprising:

• providing an intermediate VFET structure comprising a substrate, a plurality of fin structures formed thereon, and a doped layer formed on the substrate between the fin structures, the doped layer comprising a bottom source/drain (S/D) region, a bottom surface of the fin structures and a bottom surface of the doped layer being on a same plane;
• forming a shallow trench through the doped layer and the substrate below a top surface of the substrate and between the fin structures, to isolate the fin structures from each other;
• filling the shallow trench and a space between the fin structures with an insulating material;
• etching the insulating material filled between the fin structures above a level of a top surface of the doped layer, except in the shallow trench, such that a shallow trench isolation (STI) structure having a top surface at or above the level of the top surface of the doped layer is formed in the shallow trench;
• forming a plurality of gate structures on the fin structures, respectively;
• and
• forming a top S/D region above the fin structures,
• wherein the etching the insulating material is performed such that the insulating material at a position above the shallow trench is delay-etched compared to the insulating material at positions between the shallow trench and the fin structures.

A method for manufacturing a vertical field effect transistor (VFET) device, the method comprising:

• providing an intermediate VFET structure comprising a substrate, a plurality of fin structures formed thereon, and a doped layer formed on the substrate between the fin structures, the doped layer comprising a bottom source/drain (S/D) region, a bottom surface of the fin structures and a bottom surface of the doped layer being on a same plane;
• forming a shallow trench through the doped layer and the substrate below a top surface of the substrate and between the fin structures, to isolate the fin structures from each other;
• filling the shallow trench and a space between the fin structures with an insulating material;
• etching the insulating material filled between the fin structures above a level of a top surface of the doped layer, except in the shallow trench, such that a shallow trench isolation (STI) structure having a top surface at or above the level of the top surface of the doped layer is formed in the shallow trench;
• forming a plurality of gate structures on the fin structures, respectively;
• and
• forming a top S/D region above the fin structures,
• wherein the method further comprises forming a bottom spacer on the doped layer between the fin structure and on the top surface of the STI structure after the etching the insulating material.

A method for manufacturing a vertical field effect transistor (VFET) device, the method comprising:

• providing an intermediate VFET structure comprising a substrate, a plurality of fin structures formed thereon, and a doped layer formed on the substrate between the fin structures, the doped layer comprising a bottom source/drain (S/D) region;
• forming a shallow trench through the doped layer and the substrate below a top surface of the substrate and between the fin structures, to isolate the fin structures from each other;
• filling a space between the fin structures including the shallow trench with an insulating material;
• etching the insulating material such that the insulating material filled between the fin structure and above the shallow trench is delay-etched compared to the insulating material filled in positions between the shallow trench and the fin structures to form a shallow trench isolation (STI) structure in the shallow trench;
• forming a plurality of gate structures on the fin structures, respectively;
• and
• forming a top S/D region above the fin structure.

A vertical field effect transistor (VFET) device comprising:

• a substrate;
• a doped layer formed on the substrate by doping impurities, the doped layer comprising a bottom source/drain (S/D) region;
• a bottom spacer formed on the doped layer;
• a plurality of fin structures vertically formed on the substrate above the doped layer;
• a plurality gate structures respectively surrounding the fin structures;
• a top S/D region formed above the fin structures;
• a shallow trench isolation (STI) structure filling a shallow trench formed through the doped layer and the substrate below a top surface of the substrate and between the fin structures and
• an interlayer dielectric (ILD) structure separately formed above the STI structure and between the gate structures,
• wherein a top surface of the STI structure is at or above a level of a top surface of the bottom spacer,
• wherein a bottom surface of the fin structures and a bottom surface of the doped layer are on a same plane.

A vertical field effect transistor (VFET) device comprising:

• a substrate;
• a doped layer formed on the substrate by doping impurities, the doped layer comprising a bottom source/drain (S/D) region;
• a plurality of fin structures vertically formed on the substrate above the doped layer;
• a top S/D region formed above the fin structures;
• and
• a shallow trench isolation (STI) structure filling a shallow trench formed through the doped layer and the substrate below a top surface of the substrate and between the fin structures,
• wherein a top surface of the STI structure is at or above a level of a top surface of the doped layer,
• wherein a bottom surface of the fin structures and a bottom surface of the doped layer are on a same plane, and
• wherein the VFET further comprises a bottom spacer formed on the doped layer and the top surface of the STI structure.