Integrated CMOS source drain formation with advanced control

A method of forming a semiconductor device, the method comprising:

• performing an anisotropic etch process on a semiconductor material on a semiconductor substrate to expose a surface in the semiconductor material, the surface disposed between an existing structure of the semiconductor device and a bulk semiconductor portion of the semiconductor substrate on which the semiconductor material is formed;
• performing an isotropic etch process on an exposed sidewall to recess the semiconductor material that is disposed between the existing structure and the bulk semiconductor portion of the semiconductor substrate by a distance to form a cavity;
• in situ measuring the distance that the semiconductor material has been recessed after isotropic etch;
• forming a layer of deposited material via a selective epitaxial growth (SEG) process on a surface of the cavity, the substrate not subjected to a pre-clean process between formation of the cavity and SEG;
• adjusting the SEG process based on the distance that the semiconductor material has been recessed;
• and
• forming a doped region on the layer of deposited material via a selective epitaxial growth (SEG) process, wherein the doped region comprises one or more of phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), lithium (Li), boron (B), aluminum (Al), gallium (Ga), and indium (In), the doped region having a dopant concentration in a range of about 1×1020 atoms/cm3 to about 1×1022 atoms/cm3,
• wherein the isotropic etch process, the SEG process, and the in situ measuring are performed in a single platform under vacuum processing.