US 11,309,400 B2 · Stacked thin film transistors with nanowires

Abstract

Thin film transistor structures and processes are disclosed that include stacked nanowire bodies to mitigate undesirable short channel effects, which can occur as gate lengths scale down to sub-100 nanometer (nm) dimensions, and to reduce external contact resistance. In an example embodiment, the disclosed structures employ a gate-all-around architecture, in which the gate stack (including a high-k dielectric layer) wraps around each of the stacked channel region nanowires (or nanoribbons) to provide improved electrostatic control. The resulting increased gate surface contact area also provides improved conduction. Additionally, these thin film structures can be stacked with relatively small spacing (e.g., 1 to 20 nm) between nanowire bodies to increase integrated circuit transistor density. In some embodiments, the nanowire body may have a thickness in the range of 1 to 20 nm and a length in the range of 5 to 100 nm.

Claims20

Dependent claims

An integrated circuit (IC) comprising:

a body including an oxide semiconductor material including first, second, and third portions, the second portion between the first and third portions, the first portion being a source region and the third portion being a drain region, and the second portion having a cross-section with a maximum lateral width greater than a maximum vertical height;
a gate dielectric structure wrapped around the second portion of the body;
and
a gate electrode structure wrapped around the gate dielectric structure, the gate electrode structure comprising metal.

1 more element

Dependencies are inferred from the claim text.

Stacked thin film transistors with nanowires

Life of this patent

Stacked thin film transistors with nanowires

Life of this patent

Abstract

Claims20