US 11,309,395 B2Granted

1.5T SONOS memory structure and manufacturing method

AssigneeShanghai Huali Microelectronics Corporation

InventorXiaoliang Tang

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Abstract

The present invention provides a 1.5T SONOS memory structure and a manufacturing method, comprises a P-well and a storage well on its side, gates of a select transistor and a storage transistor; the height of the select transistor gate is less than the height of the storage transistor gate, an stack layer is between the gats of the select transistor and the storage transistor which height is same as the storage transistor gate; the top of the select transistor gate has a first sidewall; the sidewall of the select transistor gate has a second sidewall. The present invention strengthens the isolation between the gates of the select transistor and the storage transistor, reduces the risk of current leakage, enables the metal silicide to also grow on the gate of the select transistor, reduces the resistance of the select transistor and improves the performance of the device.

Claims15

Dependent claims

A 1.5T SONOS memory structure, comprising:

a P-type well and a storage well on one side of the P-type well;
a select transistor gate on the P-type well;
and
a storage transistor gate on the storage well, wherein a height of the select transistor gate is less than a height of the storage transistor gate, a sidewall of the storage transistor gate farthest from the select transistor gate is a slope, and a first metal silicide is provided on the slope;
an ONO stack layer is provided between the select transistor gate and the storage transistor gate, and a height of the ONO stack layer is the same as the height of the storage transistor gate;
a top of the select transistor gate is provided with a first sidewall relying on the ONO stack layer;
a remaining part of the top of the select transistor gate is provided with a second metal silicide;
and a sidewall of the select transistor gate farthest from the storage transistor gate is provided with a second sidewall.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/826,554Filed 23 Mar 2020
Priority: CN 201911100281.712 Nov 2019
Published: US 2021/0143259 A113 May 2021
Granted: 19 Apr 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10D 30/696
Characterised by the shapes, relative sizes or dispositions of the gate electrodes: having at least one additional gate, e.g. program gate, erase…
H10B 43/30
EEPROM devices comprising charge-trapping gate insulators: characterised by the memory core region
H10D 30/0212
Of FETs having insulated gates [IGFET]: using self-aligned silicidation
H10D 30/0413
Of FETs having insulated gates [IGFET]: of FETs having charge-trapping gate insulators, e.g. MNOS transistors

Family

US 2021/0143259 A1Pre-grant publication · published 13 May 2021
US 11,309,395 B2This patent

From the US filing history. Foreign family members aren’t listed.

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