Semiconductor memory device, memory system, and defect detection method

A defect detection method for a semiconductor memory device, wherein the semiconductor memory device includes a first wiring and a second wiring, a memory transistor connected between the first wiring and the second wiring, a first selection transistor connected between the first wiring and the memory transistor, a second selection transistor connected between the second wiring and the memory transistor, a third wiring connected to a gate electrode of the first selection transistor, and a fourth wiring connected to a gate electrode of the second selection transistor, the defect detection method comprising:

• from a first timing to a second timing, supplying a first voltage that turns the first selection transistor ON to the third wiring, and not supplying a second voltage that turns the first selection transistor OFF to the third wiring;
• from the first timing to the second timing, not supplying a third voltage that turns the second selection transistor ON to the fourth wiring, and supplying a fourth voltage that turns the second selection transistor OFF to the fourth wiring;
• from the second timing to a third timing, not supplying the first voltage to the third wiring, and supplying the second voltage to the third wiring;
• and
• at a fourth timing between the first timing and the third timing, detecting at least one of a voltage and a current of the first wiring.