Semiconductor device
AssigneeMitsubishi Electric Corporation
InventorKatsumi Satoh
Life of this patent
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Abstract
Each of a plurality of IGBT cells includes an n base layer formed in a semiconductor layer, a p base layer formed in a surface portion of the n base layer on a side of the first main surface, an n emitter layer formed in a surface portion of the p base layer, and a p collector layer formed in a surface portion of the semiconductor layer on a side of the second main surface. On a first main surface of the semiconductor layer, a gate electrode and an emitter electrode are formed. On a second main surface of the semiconductor layer, a collector electrode is formed. A pitch of the plurality of IGBT cells is 1/40 or more and 1/20 or less of a distance between the p base layer and the p collector layer.
Claims14
A semiconductor device comprising:
- a semiconductor layer having a first main surface and a second main surface;
- and
- a plurality of IGBT cells formed in the semiconductor layer,
- wherein
- each of the plurality of IGBT cells includes:
- a first semiconductor region of a first conductivity type formed in the semiconductor layer;
- a second semiconductor region of a second conductivity type formed in a surface portion of the first semiconductor region on a side of the first main surface;
- a third semiconductor region of the first conductivity type formed in a surface portion of the second semiconductor region;
- a fourth semiconductor region of the second conductive type formed in a surface portion of the semiconductor layer on a side of the second main surface;
- a gate insulating film formed on the first main surface of the semiconductor layer;
- a gate electrode formed so as to be opposed to the first semiconductor region, the second semiconductor region, and the third semiconductor region with the gate insulating film interposed;
- a first main electrode formed on the first main surface of the semiconductor layer and connected to the second semiconductor region and the third semiconductor region;
- and
- a second main electrode formed on the second main surface of the semiconductor layer and connected to the fourth semiconductor region, and
- a pitch of the plurality of IGBT cells is 1/40 or more and 1/20 or less of a distance between the second semiconductor region and the fourth semiconductor region.
A semiconductor device comprising:
- a semiconductor layer having a first main surface and a second main surface;
- and
- a plurality of IGBT cells formed in the semiconductor layer,
- wherein
- each of the plurality of IGBT cells includes:
- a first semiconductor region of a first conductivity type formed in the semiconductor layer;
- a second semiconductor region of a second conductivity type formed in a surface portion of the first semiconductor region on a side of the first main surface;
- a third semiconductor region of the first conductivity type formed in a surface portion of the second semiconductor region;
- a fourth semiconductor region of the second conductive type formed in a surface portion of the semiconductor layer on a side of the second main surface;
- a fifth semiconductor region of the first conductive type disposed between the first semiconductor region and the second semiconductor region, and having a higher peak concentration of an impurity than the first semiconductor region;
- a gate insulating film formed on the first main surface of the semiconductor layer;
- a gate electrode formed so as to be opposed to the first semiconductor region, the second semiconductor region, and the third semiconductor region with the gate insulating film interposed;
- a first main electrode formed on the first main surface of the semiconductor layer, and connected to the second semiconductor region and the third semiconductor region;
- and
- a second main electrode formed on the second main surface of the semiconductor layer, and connected to the fourth semiconductor region, and
- a pitch of the plurality of IGBT cells is 1/50 or more, and 1/20 or less of a distance between the second semiconductor region and the fourth semiconductor region.
Dependencies are inferred from the claim text.