Display panel and method of fabricating same

A display panel, comprising:

• a substrate;
• a light shielding layer disposed on the substrate;
• a buffer layer disposed on the substrate and covering the light shielding layer;
• an active layer disposed on the buffer layer;
• a gate insulating layer and a gate metal layer stacking-disposed on the active layer;
• an interlayer dielectric layer disposed on the buffer layer and covering the gate metal layer;
• a second metal layer disposed on the interlayer dielectric layer, wherein the second metal layer comprises a source/drain metal layer;
• a passivation layer and a flat layer stacking-disposed on the interlayer dielectric layer;
• an anode metal layer, a light emitting layer, and a cathode metal layer stacking-disposed on the flat layer;
• wherein the active layer comprises an active island comprising a conductor layer and a semiconductor layer aligned with and in contact with the gate insulating layer, the conductor layer is provided with a protective layer, and the source/drain metal layer passes through the protective layer to contact and connect with the conductor layer;
• and
• wherein the light shielding layer comprises a first metal electrode plate, the active layer further comprises a dielectric layer independent of the active island, the dielectric layer has a position aligned with the first metal electrode plate, and the second metal layer further comprises a second metal electrode plate disposed on the dielectric layer and independent of the source/drain metal layer.

A method of fabricating a display panel, comprising:

• a step S10 of forming a light shielding layer on a substrate and a buffer layer covering the light shielding layer, wherein the light shielding layer comprises a first metal electrode plate;
• a step S20 of forming a patterned active layer on the buffer layer, wherein the active layer comprises an active island and a dielectric layer independent of the active island, and a position of the dielectric layer is aligned with a position of the first metal electrode plate;
• a step S30 of sequentially forming a gate insulating layer and a gate metal layer in stack on the active island;
• a step S40 of conductorizing a portion of the active island exposed by the gate insulating layer to form a conductor layer, and forming a protective layer covering the conductor layer;
• a step S50 of forming an interlayer dielectric layer covering the active layer and the gate metal layer;
• a step S60 of forming a second metal layer on the interlayer dielectric layer and the dielectric layer, and patterning the second metal layer to form a source/drain metal layer in contact with and in connection with the conductor layer and a second metal electrode plate independent of the source/drain metal layer, wherein the second metal electrode plate is disposed on the dielectric layer to form a storage capacitor with the first metal electrode plate;
• a step S70 of forming a passivation layer and a flat layer in stack on the interlayer dielectric layer;
• and
• a step S80 of sequentially forming an anode metal layer, a light emitting layer, and a cathode metal layer in stack on the flat layer.