Method of manufacturing array substrate and array substrate

A method of manufacturing an array substrate, comprises steps of:

• providing a substrate;
• providing a patterned first metallic layer on the substrate, wherein the first metallic layer comprises a source electrode;
• providing a first insulating layer on the patterned first metallic layer;
• providing a patterned semiconductor layer on the first insulating layer, wherein a part of the semiconductor layer corresponding to the source electrode is electrically connected to the source electrode;
• providing a second insulating layer on the patterned semiconductor layer;
• providing a patterned second metallic layer on the second insulating layer, wherein the second metallic layer comprises a touch signal line, a gate electrode, and a drain electrode, and the drain electrode is electrically connected to a part of the semiconductor layer corresponding to the drain electrode;
• providing a planarization layer on the patterned second metallic layer;
• providing a patterned common electrode layer on the planarization layer, wherein the patterned common electrode layer comprises a touch electrode electrically connected to the touch signal line;
• providing a protecting layer on the patterned common electrode layer;
• and
• providing a patterned pixel electrode layer on the protecting layer, wherein the patterned pixel electrode layer comprises a pixel electrode electrically connected to the drain electrode;
• wherein the first metallic layer comprises a data line and a shading layer, and the data line is connected to the source electrode and integrated with the source electrode;
• and
• the data line, the source electrode, and the shading layer are formed with a same mask.

An array substrate, comprises:

• a substrate;
• a patterned first metallic layer disposed on the substrate, wherein the first metallic layer comprises a source electrode;
• a first insulating layer covering the first metallic layer, wherein the first insulating layer is provided with a first via hole corresponding to the source electrode;
• a semiconductor layer disposed on the first insulating layer, wherein a part of the semiconductor layer corresponding to the source electrode is electrically connected to the source electrode through the first via hole;
• a second insulating layer covering the semiconductor layer, wherein the second insulating layer is provided with an opening exposing a part of the semiconductor layer corresponding to a drain electrode;
• a second metallic layer disposed on the second insulating layer, wherein the second metallic layer comprises a touch signal line, a gate electrode, and the drain electrode, and the drain electrode is disposed in the opening and is electrically connected to the semiconductor layer;
• a planarization layer covering the second metallic layer, the planarization layer is provided with a second via hole exposing the touch signal line;
• a common electrode layer disposed on the planarization layer, wherein the common electrode layer comprises a touch electrode electrically connected to the touch signal line through the second via hole;
• a protecting layer covering the common electrode layer, wherein the protecting layer is provided with a third via hole corresponding to the drain electrode, extending to the planarization layer, and exposing the drain electrode;
• and
• a pixel electrode layer disposed on the protecting layer, wherein the pixel electrode layer comprises a pixel electrode electrically connected to the drain electrode through the third via hole;
• wherein the second metallic layer further comprises a gate line connected to the gate electrode and integrated with the gate electrode, and an extension direction of touch signal line is parallel to an extension direction of the gate line.