3-dimensional NOR memory array architecture and methods for fabrication thereof

A method for providing a memory structure, comprising:

• providing a semiconductor substrate having a substantially planar surface;
• providing a first stack of active strips and a second stack of active strips formed over the surface of the semiconductor substrate and separated by a predetermined distance along a first direction substantially parallel the planar surface, wherein each stack of active strips comprises two or more active strips provided one on top of another, with adjacent active strips being isolated from each other by a first dielectric layer, the active strips being substantially aligned lengthwise with each other along a second direction that is substantially also parallel to the planar surface but orthogonal the first direction, and wherein each active strip comprises a first semiconductor layer of a first conductivity type provided in one or more recessed portions of a second dielectric layer sandwiched between a second semiconductor layer and a third semiconductor layer each of a second conductivity type, the first, second and third semiconductor layers being stacked along a third direction that is substantially normal to the planar surface;
• providing a storage layer;
• and
• providing a plurality of conductors each extending lengthwise along a third direction that is substantially perpendicular to the planar surface, each conductor being within a group of the conductors that are provided between the first stack of active strips and the second stack of active strips and separated from each stack of active strips by the storage layer, thereby forming in each active strip at least one NOR string, each NOR string including a plurality of storage transistors that are formed out of the first, the second and the third semiconductor layers of the active strip and their adjacent storage layer and the conductors within the group.