Compact memory cell with a shared conductive word line and methods of making such a memory cell

A device, comprising:

• a semiconductor substrate having an upper surface;
• a first memory cell comprising a first memory gate positioned above the upper surface of the semiconductor substrate and a first gate cap above the first memory gate;
• a first sidewall spacer positioned adjacent the first memory gate;
• a second memory cell comprising a second memory gate positioned above the upper surface of the semiconductor substrate and a second gate cap above the second memory gate;
• a second sidewall spacer positioned adjacent the second memory gate;
• a conductive word line structure positioned above the upper surface of the semiconductor substrate between the first and second sidewall spacers, wherein the conductive word line structure is shared by the first and second memory cells, and wherein an upper surface of the conductive word line structure is above an upper surface of the first gate cap and an upper surface of the second gate cap, and wherein the conductive word line structure covers a portion of the upper surfaces of the first gate cap and the second gate cap leaving a portion of the upper surfaces of the first gate cap and the second gate cap exposed;
• a first conductive select gate structure for the first memory cell, the first conductive select gate structure being positioned above the upper surface of the semiconductor substrate adjacent the first sidewall spacer;
• and
• a second conductive select gate structure for the second memory cell, the second conductive select gate structure being positioned above the upper surface of the semiconductor substrate adjacent the second sidewall spacer.