Three-dimensional memory devices with drain select gate cut and methods for forming the same

A method for forming a three-dimensional (3D) memory device, comprising:

• forming a dielectric stack comprising interleaved sacrificial layers and dielectric layers above a substrate;
• removing a portion of the uppermost one of the sacrificial layers;
• simultaneously forming a first memory string and a second memory string each having nominally the same height, wherein the first memory string extends vertically through a first region of the dielectric stack comprising a remainder of the uppermost sacrificial layer, and the second memory string extends vertically through a second region of the dielectric stack free of the uppermost sacrificial layer;
• forming a memory stack comprising interleaved conductive layers and the dielectric layers by replacing the sacrificial layers of the dielectric stack with the conductive layers;
• and
• forming a first bit line contact and a second bit line contact above and in contact with the first memory string and the second memory string, respectively.

A method for forming a three-dimensional (3D) memory device, comprising:

• forming a dielectric stack comprising interleaved sacrificial layers and dielectric layers above a substrate;
• removing a portion of the uppermost one of the sacrificial layers;
• simultaneously forming a first channel structure and a second channel structure, wherein the first channel structure extends vertically through a first region of the dielectric stack comprising a remainder of the uppermost sacrificial layer, and the second channel structure extends vertically through a second region of the dielectric stack free of the uppermost sacrificial layer;
• forming an elevating layer on the first region, but not the second region, of the dielectric stack;
• simultaneously forming a first recess through the elevating layer into a top portion of the first channel structure, and a second recess into a top portion of the second channel structure;
• and
• simultaneously forming a first channel plug and a second channel plug in the first recess and the second recess, respectively.

A three-dimensional (3D) memory device, comprising:

• a memory stack comprising vertically interleaved conductive layers and dielectric layers;
• a plurality of memory strings each extending vertically through the memory stack;
• and
• a plurality of bit line contacts, each of the plurality of the memory strings being in contact with a respective one of the plurality of bit line contacts,
• wherein:
• the plurality of memory strings are divided into a plurality of regions of the memory stack in a plan view;
• the conductive layers comprise a plurality of drain select gate (DSG) lines configured to control drains of the plurality of memory strings;
• numbers of the DSG lines through which the plurality of memory strings extend vertically are different among the plurality of regions, the drains of the plurality of memory strings in different regions of the plurality of regions being controlled by different numbers of the DSG lines;
• numbers of the plurality of memory strings are the same among the plurality of regions;
• and
• each of the plurality of memory strings has a nominally same height.