Integrated structures containing vertically-stacked memory cells

An integrated structure comprising:

• a stack of alternating dielectric levels comprising a dielectric material and conductive levels that comprise a conductive material that physically contacts the dielectric material;
• vertically-stacked memory cells within the conductive levels, each of the vertically stacked memory cells comprising a charge trapping region, the dielectric material of the dielectric levels extending over and beneath the charge trapping region across an entirety of a width of the charge trapping region;
• an opening extending through the stack, the opening having a sidewall extending vertically continuously from top to bottom of the opening;
• and
• a first channel material liner within the opening and along the memory cells and directly against the dielectric material of the dielectric levels, the first channel material liner comprising tin oxide having a thickness of from one monolayer to 60 Angstroms;
• and
• a second channel material comprising germanium within the opening and spaced from the sidewall by the first channel material.