Structures and SRAM bit cells integrating complementary field-effect transistors

A method of forming a static random access memory (SRAM) bit cell, the method comprising:

• forming a first inverter that includes a first complementary field-effect transistor, wherein a first source/drain region of the first complementary field-effect transistor is formed on an isolation layer comprised of a first dielectric material, and a second source/drain region of the first complementary field-effect transistor is formed over the first source/drain region;
• etching an opening extending through the first source/drain region and the second source/drain region to the isolation layer;
• depositing a second dielectric material in the opening to define a pillar;
• forming a second inverter that is cross-coupled with the first inverter;
• forming a first pass-gate transistor coupled with the first inverter;
• and
• forming a second pass-gate transistor coupled with the second inverter,
• wherein the first complementary field-effect transistor has a first shared gate electrode, the second inverter includes a second complementary field-effect transistor having a second shared gate electrode, the first pass-gate transistor has a third gate electrode, the second pass-gate transistor has a fourth gate electrode, and the first shared gate electrode, the second shared gate electrode, the third gate electrode, and the fourth gate electrode are arranged in a 1CPP layout.