Semiconductor structure having a dummy gate with an interlayer dielectric layer therein

A semiconductor structure comprising:

• a base substrate including a first region, a second region and a third region between the first and second region;
• a dummy gate structure extending across the first region and the second region and dummy gate sidewall spacers surrounding the dummy gate structure;
• first doped source/drain regions in the base substrate on both sides of the dummy gate structure in the first region;
• second doped source/drain regions in the base substrate on both sides of the dummy gate structure in the second region;
• an interlayer dielectric layer in the dummy gate structure in the third region and on the base substrate in the third region, wherein the interlayer dielectric layer has a top surface higher than a top surface of the dummy gate structure;
• a first sidewall spacer formed on the sidewalls of the interlayer dielectric layer;
• and
• a second sidewall spacer on the first sidewall spacer.