Digit line formation for horizontally oriented access devices

A method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines, comprising:

• forming layers of a first dielectric material, a low doped semiconductor material, and a second dielectric material, in repeating iterations vertically to form a vertical stack;
• forming a vertical opening in the vertical stack;
• selectively etching the second dielectric material to form a first horizontal opening in the second dielectric material having a first distance horizontally back from the vertical opening;
• gas phase doping a dopant into a top surface of the low doped semiconductor material in the first horizontal opening to form a source/drain region;
• forming a first high doped semiconductor material in the first horizontal opening;
• selectively etching the first high doped semiconductor material formed in the first horizontal opening such that a portion of the first high doped semiconductor material formed in the first horizontal opening;
• converting the remaining first high doped semiconductor material to a conductive material having a different characteristic from the remaining high doped semiconductor material, wherein the source/drain region remains intact during the conversion;
• selectively etching the source/drain region and the low doped semiconductor material to form a second horizontal opening having a second distance horizontally back from the vertical opening;
• forming a third dielectric material in the second horizontal opening;
• and
• forming a second high doped semiconductor material in the vertical opening.

A memory cell array, comprising:

• a plurality of access transistors stacked on one another, each of the access transistors including a first source/drain region, a second source/drain region and a channel region therebetween which are horizontally arranged, and a body region;
• at least one access line elongating vertically and coupled to each of the channel regions of the plurality of access transistors with an intervention of a gate dielectric;
• a plurality of storage capacitors stacked on one another, each of the plurality of storage capacitors lying horizontally and coupled to a corresponding one of the second source/drain regions of the plurality of access transistors;
• a plurality of digit lines, each of the plurality of digit lines coupled to a corresponding one of the first source/drain regions of the plurality of access transistors;
• and
• a body contact elongating vertically and coupled to each of the body regions of the plurality of access transistors.