Methods of resistance and capacitance reduction to circuit output nodes

An integrated circuit, comprising:

• a plurality of active areas;
• a plurality of gates crossing over the plurality of active areas;
• a plurality of conductive patterns each arranged between two of the plurality of gates and crossing over the plurality of active areas;
• at least one first conductive segment disposed above the plurality of conductive patterns;
• a plurality of vias comprising a first via and a second via, wherein the first via includes a first area contacting the at least one first conductive segment, and a second area contacting a first conductive pattern of the plurality of conductive patterns, the first conductive pattern corresponds to an output node of the integrated circuit, and the first area is greater than the second area;
• and
• at least one power rail pattern disposed above the plurality of conductive patterns and coupled through the second via to one of the plurality of conductive patterns;
• wherein the first via and the second via have a substantially same resistance value.

An integrated circuit, comprising:

• a first conductive pattern and a second conductive pattern that are disposed in a first layer and extend in a first direction,
• wherein the first and second conductive patterns are associated with two terminals, of first and second transistors, that are coupled with each other at an output node of the integrated circuit;
• at least one first conductive segment disposed in a second layer different from the first layer;
• and
• at least one via disposed between the first layer and the second layer, wherein the at least one via is coupled between the at least one first conductive segment, configured as the output node of the integrated circuit, and one or both of the first conductive pattern and the second conductive pattern,
• wherein the at least one via comprises a tapered shape with a width that decreases from a first width to a second width narrower than the first width;
• wherein the first width of the at least one via is greater than widths of the first conductive pattern and the second conductive pattern.