Stack-gate circuit

An integrated circuit comprising:

• an active zone, extending in a first direction, including a center portion adjoining a first side portion and a second side portion;
• a plurality of conductive segments extending in a second direction that is perpendicular to the first direction;
• a plurality of gate-strips extending in the second direction and conductively connected together, wherein the plurality of gate-strips includes,
• a first group of gate-strips intersecting the active zone over first channel regions in the center portion,
• a second group of gate-strips intersecting the active zone over second channel regions in the center portion,
• a third group of gate-strips intersecting the active zone over third channel regions in the first side portion, and
• a fourth group of gate-strips intersecting the active zone over fourth channel regions in the second side portion;
• wherein a first transistor having a gate formed over one of the first channel regions has a first threshold-voltage, a second transistor having a gate formed over one of the second channel regions has a second threshold-voltage, a third transistor having a gate formed over one of the third channel regions has a third threshold-voltage, and a fourth transistor having a gate formed over one of the fourth channel regions has a fourth threshold-voltage;
• and
• wherein a first difference between the first threshold-voltage and the second threshold-voltage is less than 10% of a first average of the first threshold-voltage and the second threshold-voltage, a second difference between the third threshold-voltage and the fourth threshold-voltage is less than 10% of a second average of the third threshold-voltage and the fourth threshold-voltage, and the first average is larger than the second average by a predetermined threshold-voltage offset.

An integrated circuit comprising:

• an active zone, extending in a first direction, including a center portion adjoining a first side portion and a second side portion;
• a plurality of conductive segments extending in a second direction that is perpendicular to the first direction;
• a plurality of gate-strips extending in the second direction and conductively connected together, wherein the plurality of gate-strips includes,
• a first group of gate-strips intersecting the active zone over first channel regions in the center portion,
• a second group of gate-strips intersecting the active zone over second channel regions in the center portion,
• a third group of gate-strips intersecting the active zone over third channel regions in the first side portion, and
• a fourth group of gate-strips intersecting the active zone over fourth channel regions in the second side portion;
• wherein a first transistor having a gate formed over one of the first channel regions has a first threshold-voltage, a second transistor having a gate formed over one of the second channel regions has a second threshold-voltage, a third transistor having a gate formed over one of the third channel regions has a third threshold-voltage, and a fourth transistor having a gate formed over one of the fourth channel regions has a fourth threshold-voltage;
• a routing line, extending in the first direction, conductively connecting to each gate-strip in the plurality of gate-strips through a type-one via;
• and
• wherein each of the first transistor and the second transistor is a high-threshold transistor, and each of the third transistor and the fourth transistor is a low-threshold transistor, and wherein a threshold-voltage of the high-threshold transistor is larger than a threshold-voltage of the low-threshold transistor.