Semiconductor package including stacked semiconductor chips

A semiconductor package, comprising:

• a substrate;
• a sub semiconductor package disposed over the substrate and including:
• a sub semiconductor chip which has chip pads on its active surface facing the substrate;
• a sub molding layer which surrounds side surfaces of the sub semiconductor chip and has one surface facing the substrate;
• and
• redistribution conductive layers which are connected to the chip pads and extend over the one surface of the sub molding layer, wherein the redistribution conductive layers include:
• a signal redistribution conductive layer which extends onto an edge of the sub molding layer and has a signal redistribution pad on its end portion;
• and
• a power redistribution conductive layer which has a length shorter than a length of the signal redistribution conductive layer and has a power redistribution pad on its end portion;
• a signal sub interconnector having an upper surface connected to the signal redistribution pad and a lower surface connected to the substrate;
• a power sub interconnector having an upper surface connected to the power redistribution pad and a lower surface connected to the substrate;
• a capacitor formed in the sub molding layer and including:
• a first electrode with a lower surface connected to the power redistribution conductive layer;
• a second electrode with a lower surface connected to the power redistribution conductive layer;
• and
• a body portion between the first electrode and the second electrode;
• and
• at least one main semiconductor chip formed over the sub semiconductor package and electrically connected to the substrate.