Semiconductor apparatus including penetration electrodes connecting laminated semiconductor chips
AssigneesHonda Motor Co., Ltd., Tokyo Institute of Technology
InventorsKoji Sakui, Takayuki Ohba
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Abstract
A semiconductor apparatus according to an embodiment of the present invention includes: a plurality of semiconductor chips that are laminated; and a plurality of penetration electrodes that penetrate in a lamination direction through the plurality of semiconductor chips and that electrically connect together the plurality of semiconductor chips, wherein a semiconductor chip has at least one sub-memory array, and a penetration electrode penetrates through an outer circumferential part of the sub-memory array.
Claims6
A semiconductor apparatus comprising:
- a plurality of semiconductor chips that are laminated;
- and
- a plurality of penetration electrodes that penetrate in a lamination direction through the plurality of semiconductor chips and that electrically connect together the plurality of semiconductor chips,
- wherein a semiconductor chip of the plurality of semiconductor chips has at least one sub-memory array,
- a penetration electrode of the plurality of penetration electrodes penetrates through an outer circumferential part of the sub-memory array, and
- in the semiconductor chip, positions at which the penetration electrode penetrates are distributed so as to constitute a plurality of rows along the outer circumferential part.
A semiconductor apparatus, comprising:
- a plurality of semiconductor chips that are laminated;
- and
- a plurality of penetration electrodes that penetrate in a lamination direction through the plurality of semiconductor chips and that electrically connect together the plurality of semiconductor chips,
- wherein a semiconductor chip of the plurality of semiconductor chips has at least one sub-memory array,
- a penetration electrode of the plurality of penetration electrodes penetrates through an outer circumferential part of the sub-memory array, and
- the semiconductor chip has a replacement sub-memory array.
Dependencies are inferred from the claim text.