Three-dimensional stacking semiconductor assemblies and methods of manufacturing the same

A semiconductor device package, comprising:

• a semiconductor substrate having an active side and an inactive side opposite the active side, the substrate including
• a first metallization layer positioned at the active side,
• a second metallization layer at least partially embedded in the substrate and electrically coupled to the first metallization layer, wherein
• the inactive side of the substrate includes a divot exposing a portion of the second metallization layer for providing an external electrical connection;
• a metal bump protruding away from the active side, directly aligned with the divot, and electrically coupled to the first metallization layer;
• a dielectric layer formed at the inactive side of the substrate, the dielectric layer having a dielectric opening within the divot and over the exposed portion of the second metallization layer;
• and
• a barrier layer disposed between the dielectric layer and the second metallization layer, the barrier layer including a barrier opening over the exposed portion of the second metallization layer.

A semiconductor device package assembly, comprising:

• a base substrate having a first side and a second side opposite the first side, the base substrate having a first set of metallization layers at the first side, the first set of metallization layers having a contacting area;
• and
• at least one semiconductor device package stacked on the base substrate, each of the at least one semiconductor device package having
• an active side and an inactive side,
• a second set of metallization layers at the active side, wherein
• a portion of the second set of metallization layers is exposed through a divot in the inactive side, and
• the second set of metallization layers is electrically coupled directly to the first set of metallization layers and without using a through-silicon via (TSV),
• a metal bump in the divot and electrically coupled to the second set of metallization layers, wherein the metal bump is electrically coupled to the first set of metallization layers at the contacting area;
• and
• wherein the at least one semiconductor device package has a depth not more than 30 μm.

A method of manufacturing a semiconductor device package, comprising:

• forming a semiconductor substrate having an active side and an inactive portion opposite the active side;
• forming first and second metallization layers in the substrate at the active side, the first and second metallization layers being separated across at least a portion of a thickness of the semiconductor substrate and electrically coupled to each other without using a through-silicon via (TSV);
• forming a metal bump electrically coupled to the first metallization layer;
• and
• thinning the semiconductor substrate to a depth not more than 30 μm based on removing a portion of the inactive portion;
• forming a divot at a surface of the remaining inactive portion of the substrate, the divot being directly aligned with the metal bump;
• and
• exposing a portion of the second metallization layer through the divot, wherein the exposed portion is configured to provide a direct electrical connection to an external circuit.