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US 11,309,246 B2Granted
High density 3D interconnect configuration
AssigneeApple Inc.
InventorsSanjay Dabral, Zhitao Cao, Kunzhong Hu, Jun Zhai
Life of this patent
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Abstract
Electronic package structures and systems are described in which a 3D interconnect structure is integrated into a package redistribution layer and/or chiplet for power and signal delivery to a die. Such structures may significantly improve input output (IO) density and routing quality for signals, while keeping power delivery feasible.
Claims20
An electronic package comprising:
- a redistribution layer (RDL);
- a die coupled to the RDL;
- wherein the RDL includes a 3D interconnect structure for power and signal delivery to the die;
- a chiplet on a second side of the RDL opposite the die;
- and
- wherein the die includes a low performance logic and a high performance logic, and the chiplet is substantially directly underneath the low performance logic.
3 more elements
An electronic package comprising:
- a redistribution layer (RDL);
- a die coupled to the RDL;
- wherein the RDL includes a 3D interconnect structure for power and signal delivery to the die:
- a chiplet, wherein the chiplet is at least partially directly underneath the die and comprises a power mesh plane;
- wherein the 3D interconnect structure comprises a power bar underneath a plurality of contact pads, the power bar to supply a positive power supply to the die, wherein the die is bonded to the plurality of contact pads;
- and
- wherein the power mesh plane is electrically coupled to the power bar.
4 more elements
An electronic system comprising:
- a circuit board, the circuit board including a negative power supply (Vss) landing pad, a positive power supply (Vdd) landing pad, and a plurality of signal landing pads;
- an electronic package mounted on the circuit board and bonded to the Vss landing pad, the Vdd landing pad, and the plurality of signal landing pads;
- wherein the electronic package includes:
- a redistribution layer (RDL);
- and
- a die on the RDL;
- and
- a 3D interconnect structure for Vss, Vdd, and signal delivery to the die;
- a chiplet on a second side of the RDL opposite the die, wherein the chiplet is at least partially directly underneath the die, and the chiplet comprises a power mesh plane;
- wherein the 3D interconnect structure comprises:
- a power bar underneath a plurality of contact pads, the power bar coupled to the Vdd landing pad, wherein the die is bonded to the plurality of contact pads;
- and
- wherein the power mesh plane is electrically coupled to the power bar.
10 more elements
Dependencies are inferred from the claim text.