Power semiconductor package having integrated inductor, resistor and capacitor

A power semiconductor package comprising:

• a lead frame comprising
• a first die paddle;
• a second die paddle;
• and
• a first end paddle;
• a low side field-effect transistor (FET) having a bottom surface drain electrode attached to the first die paddle, the low side FET comprising a source electrode and a gate electrode on a top surface of the low side FET;
• a high side FET having a bottom surface drain electrode attached to the second die paddle, the high side FET comprising a source electrode and a gate electrode on a top surface of the high side FET;
• a first plurality of bonding wires connecting the source electrode of the high side FET to the first die paddle;
• an inductor assembly, a first terminal of the inductor assembly being attached to the second die paddle, and a second terminal of the inductor assembly being attached to the first end paddle;
• a first conductive material comprising
• a top surface directly attached to the first terminal of the inductor assembly;
• and
• a bottom surface directly attached to the first die paddle;
• a second conductive material comprising
• a top surface directly attached to the second terminal of the inductor assembly;
• and
• a bottom surface directly attached to the first end paddle;
• and
• a molding encapsulation enclosing the low side FET, the high side FET, the first plurality of bonding wires, the inductor assembly, and a majority portion of the lead frame.

A power semiconductor package comprising:

• a lead frame comprising
• a first die paddle;
• and
• a second die paddle;
• a first lead comprising
• a first elevated section comprising
• a first end paddle;
• a second lead comprising
• a second elevated section comprising
• a second end paddle, wherein the first end paddle and the second end paddle being disposed higher than the first die paddle and the second die paddle;
• a low side field-effect transistor (FET) having a bottom surface drain electrode attached to the first die paddle, the low side FET comprising a source electrode and a gate electrode on a top surface of the low side FET;
• a high side FET having a bottom surface drain electrode attached to the second die paddle, the high side FET comprising a source electrode and a gate electrode on a top surface of the high side FET;
• a first plurality of bonding wires connecting the top surface source electrode of the high side FET to the first die paddle;
• an inductor assembly comprising a first terminal and a second terminal, the first terminal stacking on the first end paddle and the second terminal stacking on the second end paddle;
• a first conductive material comprising
• a top surface directly attached to the inductor assembly;
• and
• a bottom surface directly attached to the first end paddle;
• a second conductive material comprising
• a top surface directly attached to the inductor assembly;
• and
• a bottom surface directly attached to the second end paddle;
• and
• a molding encapsulation enclosing the low side FET, the high side FET, the first plurality of bonding wires, the first end paddle, the second end paddle, and the inductor assembly.