Single metallization scheme for gate, source, and drain contact integration
AssigneeInternational Business Machines Corporation
InventorsAndrew Greene, Victor W. C. Chan, Gangadhara Raja Muthinti
Life of this patent
Estimating the term…
Abstract
A technique relates to a semiconductor device. One or more N-type field effect transistor (NFET) gates and one or more P-type field effect transistor (PFET) gates are formed. Source and drain (S/D) contacts are formed, at least one material of the S/D contacts being formed in the PFET gates. Insulating material is deposited as self-aligned caps above the NFET gates and the PFET gates, while the insulating material is also formed as insulator portions adjacent to the S/D contacts. Middle of the line (MOL) contacts are formed above the S/D contacts.
Claims20
A semiconductor device comprising:
- one or more N-type field effect transistor (NFET) gates and one or more P-type field effect transistor (PFET) gates;
- source and drain (S/D) contacts coupled to epitaxial S/D regions, at least one material of the S/D contacts being formed in the PFET gates;
- insulating material formed as self-aligned caps directly above the NFET gates and the PFET gates;
- and
- middle of the line (MOL) contacts formed above the S/D contacts, at least one of the MOL contacts comprising a downward extended portion in direct contact with one of the S/D contacts, wherein the insulating material is also formed as insulator portions in direct contact with sides of the downward extended portion and immediately above the epitaxial S/D regions.
Dependencies are inferred from the claim text.