Methods, apparatus, and manufacturing system for self-aligned patterning of a vertical transistor

A system, comprising:

• a semiconductor device processing system to manufacture a semiconductor device comprising at least one field effect transistor (FET);
• and
• a processing controller operatively coupled to said semiconductor device processing system, said processing controller configured to control an operation of said semiconductor device processing system;
• wherein said semiconductor device processing system is adapted to:
• form a plurality of fins on a substrate, wherein each fin comprises a first side, a second side, and a hard mask on a top of the fin, wherein the hard mask has a top surface;
• form a bottom spacer on the substrate and between each pair of adjacent fins, wherein the bottom spacer is in contact with the first side and the second side of each fin;
• form a gate structure in contact with the first side of each fin from a first height below the top surface of the hard mask to the bottom spacer and in contact with the second side of each fin from the first height to the bottom spacer, wherein said gate structure comprises a high-k dielectric layer in contact with said fin, a work function metal (WFM) layer in contact with said high-k dielectric layer, and a nitride layer in contact with said WFM layer;
• form a side spacer in contact with the first side of each fin from the top surface of the hard mask to the first height and in contact with the second side of each fin from the top surface to the first height;
• form at least one layer above said bottom spacer and between said fins;
• and
• form an opening in said at least one layer between said fins by an etching process, wherein said side spacer protects said gate structure from said etching process.