Large grain copper interconnect lines for MRAM

A method of forming large grain copper bitlines for an electronic structure, comprising:

• obtaining an MRAM structure including:
• vertical pillars having a pitch of sixty nanometers or more, each of the vertical pillars including a magnetic tunnel junction and a top electrode;
• a plurality of spaces respectively between and separating each of the vertical pillars;
• and
• a dielectric layer filling each of the plurality of spaces between the vertical pillars;
• forming a copper bitline over the top electrodes and along the pitch of the vertical pillars and extending over the spaces between the vertical pillars, the copper bitline having a width of forty nanometers or less, an area of three thousand square nanometers or less, and copper grains having relatively small sizes with respect to the width of the copper bitline;
• laser annealing the copper bitline, thereby melting the copper bitline;
• and
• recrystallizing the copper bitline during a cool down period following the laser annealing, thereby forming relatively large grains therein that are vertically aligned, respectively, with the vertical pillars and having grain boundaries located mostly over the dielectric layer in the spaces between the vertical pillars.