Power loss test engine device and method
AssigneeMicron Technology, Inc.
InventorsClaudio Giaccio, Ferdinando Pascale, Raffaele Mastrangelo, Erminio Di Martino, Ferdinando D'Alessandro, Cristiano Castellano, Andrea Castaldo
Life of this patent
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Abstract
Apparatus and methods are disclosed, including test systems for memory devices. Example test systems and methods include power loss logic to determine when one or more test conditions have been met in a memory operation between a host device and a memory device under test. Example test systems and methods include a function to then instruct a power management device to trigger a power loss event.
Claims17
A test system, comprising:
- a power management device configured to selectively trigger a power loss event in a memory device under test;
- a host device, including a host driver, wherein the host device is coupled to the power management device;
- and
- power loss logic in the host device to determine when one or more test conditions have been met in a memory operation between the host device and the memory device under test, and instruct the power management device to trigger the power loss event as determined by the one or more test conditions, wherein the test conditions in the power loss logic include recognition of an external trigger to cause the power management device to initiate a power loss to the memory device under test, the external trigger originating outside the power loss logic.
A test system, comprising:
- a power management device configured to selectively trigger a power loss event in a memory device under test;
- a host device, including a host driver, wherein the host device is coupled to the power management device;
- power loss logic in the host device to determine when one or more test conditions have been met in a memory operation between the host device and the memory device under test, and instruct the power management device to trigger the power loss event as determined by the one or more test conditions, wherein the test conditions in the power loss logic include recognition of an external trigger to cause the power management device to initiate a power loss to the memory device under test, the external trigger originating outside the power loss logic;
- and a number of registers in the host device to track the one or more test conditions in the memory operation and whether or not a power loss event was triggered.
A method of testing a memory device, comprising:
- setting a test protocol in a host device, wherein the test protocol checks for one or more test conditions in a memory operation between the host device and a memory device under test;
- triggering a power loss in the memory device under test if selected test conditions have been met, wherein the test conditions in the power loss logic include recognition of an external trigger to cause the power management device to initiate a power loss to the memory device under test, the external trigger originating outside the power loss logic;
- and
- recording the one or more test conditions as they occur to make a record of a chain of events associated with triggering the power loss in the memory device under test.
Dependencies are inferred from the claim text.