US 11,309,053 B2Granted

Semiconductor memory device and storage device

AssigneeKioxia Corporation

InventorsTakehisa Kurosawa, Koichi Shinohara, Yusuke Tanefusa

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Abstract

According to one embodiment, a semiconductor memory device includes a memory cell array, a processing circuit, a timer, a command decoder, and a training circuit. The memory cell array includes a plurality of memory cells. The processing circuit writes data into the memory cell array. The timer sets a waiting time. The command decoder receives a command output from a memory controller. The training circuit waits until the waiting time has passed since a predetermined command is received by the command decoder and performs a process relating to determination of a correction value for a signal sent from the memory controller to the processing circuit based on reference data output from the memory controller after the waiting time has passed.

A storage device comprising:

a first semiconductor memory device;
and
a second semiconductor memory device;
and
a memory controller configured to control the first semiconductor memory device and the second semiconductor memory device,
wherein the memory controller is configured to output reference data after issuing a predetermined command to the first semiconductor memory device and the second semiconductor memory device,
the first semiconductor memory device includes:
a first memory cell array including a plurality of memory cells;
a first processing circuit configured to write data into the first memory cell array;
a first timer configured to set a first waiting time;
a first command decoder configured to receive a command output from the memory controller;
and
a first training circuit configured:
to wait until the first waiting time has passed since the predetermined command is received by the first command decoder, and
to perform a first process relating to determination of a correction value for a signal, which has been sent from the memory controller to the first processing circuit, based on the reference data after the first waiting time has passed,
wherein the second semiconductor memory device includes:
a second memory cell array including a plurality of memory cells;
a second processing circuit configured to write data into the second memory cell array;
a second timer configured to set a second waiting time;
a second command decoder configured to receive a command output from the memory controller;
and
a second training circuit configured:
to wait until the second waiting time has passed since the predetermined command is received by the second command decoder, and
to perform a second process relating to the determination of a correction value for a signal, which has been sent from the memory controller to the second processing circuit, based on the reference data after the second waiting time has passed, and
the second waiting time is longer than the first waiting time.

22 more elements

Facts

Application

17/009,404Filed 1 Sep 2020

Priority

JP JP2019-16721513 Sep 2019

Published

US 2021/0082536 A118 Mar 2021

Granted

19 Apr 2022

Term ends

Not estimatedThe source records don’t support an estimate.

Classification7 codes

G11C 29/44
Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details: indication or identification of errors, e.g. for…
G11C 29/028
Detection or location of defective auxiliary circuits, e.g. defective refresh counters: with adaption or trimming of parameters
G11C 29/12015
Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details: comprising clock generation or timing circuitry
G11C 29/14
Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details: implementation of control logic, e.g. test mode…

Abstract

Claims12