Direct memory access using JTAG cell addressing

An apparatus, comprising:

• a system-on-chip (SoC) device;
• a non-volatile memory device having a structurally independent structure from the SoC device;
• an interconnection pin of the non-volatile memory device coupled to an interconnection pin of the SoC device;
• a memory array in the memory device including a plurality of independently addressable sub arrays;
• sense amplifiers coupled to corresponding outputs of the sub arrays and coupled to a communication channel of the SoC device;
• and
• a scan chain comprising modified Joint Test Action Group (JTAG) cells coupled in parallel between an output of the sense amplifiers and the communication channel to perform read operations in a direct memory access, wherein the apparatus is configured to fill the communication channel with an enlarged memory page including data, corresponding address bits, and ECC bits of each sub array of the plurality of sub arrays.

An integrated circuit, comprising:

• an array of memory cells including a plurality of independently addressable sub arrays;
• sense amplifiers coupled to corresponding outputs of the sub arrays and coupled to a communication channel of a system-on-chip (SoC);
• and
• a scan chain formed by modified Joint Test Action Group (JTAG) cells coupled in parallel between an output of the sense amplifiers and the communication channel to perform read operations in a direct memory access, wherein the integrated circuit is configured to fill the communication channel with an enlarged memory page including data, corresponding address bits, and ECC bits of each sub array of the plurality of sub arrays.