Test circuit using clock signals having mutually different frequency
AssigneeMicron Technology, Inc.
InventorYutaka Uemura
Life of this patent
Estimating the term…
Abstract
Disclosed herein is an apparatus that includes first and second shift register circuits coupled in series, the first and second shift register circuits being configured to perform a shift operation of a trigger signal in synchronization with a clock signal, and a clock control circuit configured to set a frequency of the clock signal to a first frequency when the trigger signal is in the first shift register circuit and set a frequency of the clock signal to a second frequency different from the first frequency when the trigger signal is in the second shift register circuit.
Claims20
An apparatus comprising:
- first and second shift register circuits coupled in series, the first and second shift register circuits being configured to perform a shift operation of a trigger signal in synchronization with a clock signal;
- and
- a clock control circuit configured to set a frequency of the clock signal to a first frequency when the trigger signal is in the first shift register circuit and set a frequency of the clock signal to a second frequency different from the first frequency when the trigger signal is in the second shift register circuit.
An apparatus comprising:
- a first clock generator configured to generate, when activated, a first clock signal responsive to an external clock signal;
- a second clock generator configured to generate, when activated, a second clock signal irrespective of the external clock signal;
- and
- a BIST engine configured to produce a first internal command responsive to the first clock signal and a second internal command responsive to the second clock signal.
An apparatus comprising:
- a memory cell array;
- an access control circuit configured to access the memory cell array by using an internal address signal and a plurality of internal commands including a predetermined internal command;
- and
- a test circuit configured to supply the internal address signal and the plurality of internal commands to the access control circuit,
- wherein the test circuit is configured to operate in synchronization with a first clock signal having a first frequency before supplying the predetermined internal command and operate in synchronization with a second clock signal having a second frequency different from the first frequency after supplying the predetermined internal command.
Dependencies are inferred from the claim text.