Back to results
US 11,309,046 B2Granted
Semiconductor devices and semiconductor systems including the same
AssigneeSK hynix Inc.
InventorSun Myung Choi
Life of this patent
Estimating the term…
Abstract
A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs an error check enablement signal, an input clock signal, and input data to the second semiconductor device. The first semiconductor device receives an error check signal from the second semiconductor device. The second semiconductor device performs an error check operation for the input data based on the error check enablement signal and the input clock signal to generate the error check signal which is enabled when an error in the input data occurs.
Claims24
A semiconductor system comprising:
- a first semiconductor device configured to output an error check enablement signal, an input clock signal, and input data and configured to receive an error check signal;
- and
- a second semiconductor device configured to perform an error check operation for the input data based on the error check enablement signal and the input clock signal to generate the error check signal,
- wherein the error check signal is disabled when an error in the input data repeatedly occurs a first predetermined number of times or more to avoid unnecessary checks, and
- wherein the second semiconductor device comprises an error check circuit, the error check circuit comprising:
- a control circuit configured to generate a tolerance control signal, a window control signal, and a window reset signal based on the input clock signal, a first mode signal, a second mode signal, the error check enablement signal, a error detection signal, and a tolerance reset signal;
- a flag signal generation circuit configured to generate an error flag signal and the tolerance reset signal when the tolerance control signal and the window control signal are inputted a predetermined number of times;
- an error check signal generation circuit configured to control an output of the error detection signal.
5 more elements
A semiconductor system comprising:
- a first semiconductor device configured to output a first error check enablement signal, a second error check enablement signal, a first input clock signal, a second input clock signal, first input data, and second input data and configured to receive a first error check signal and a second error check signal;
- a second semiconductor device configured to perform a first error check operation for the first input data to generate the first error check signal when the first error check enablement signal and the first input clock signal are inputted to the second semiconductor device;
- and
- a third semiconductor device configured to perform a second error check operation for the second input data to generate the second error check signal when the second error check enablement signal and the second input clock signal are inputted to the third semiconductor device,
- wherein the first error check operation and the second error check operation are independently performed,
- wherein the first error check signal is disabled when an error in the first input data repeatedly occurs a predetermined number of times or more to avoid unnecessary checks;
- wherein the second error check signal is disabled when an error in the second input data repeatedly occurs the predetermined number of times or more to avoid unnecessary checks, and
- wherein the second semiconductor device comprises a first error check circuit, the first error check circuit comprising:
- a first control circuit configured to generate a first tolerance control signal, a first window control signal, and a first window reset signal based on the first input clock signal, a first mode signal, a second mode signal, the first error check enablement signal, a first error detection signal, and a first tolerance reset signal;
- a first flag signal generation circuit configured to generate a first error flag signal and the first tolerance reset signal when the first tolerance control signal and the first window control signal are inputted a predetermined number of times;
- a first error check signal generation circuit configured to control an output of the first error detection signal.
8 more elements
A semiconductor device comprising:
- a memory circuit configured to store input data provided by an external device and configured to generate an error detection signal which is enabled when an error in the input data occurs;
- and
- an error check circuit configured to perform an error check operation for the input data according to an error check enablement signal and an input clock signal provided by the external device or another external device to generate and output an error check signal according to the number of times that the error detection signal is generated,
- wherein the error check signal is disabled when an error in the input data repeatedly occurs a first predetermined number of times or more to avoid unnecessary checks, and
- wherein the error check circuit comprising:
- a control circuit configured to generate a tolerance control signal, a window control signal, and a window reset signal based on the input clock signal, a first mode signal, a second mode signal, the error check enablement signal, the error detection signal, and a tolerance reset signal;
- a flag signal generation circuit configured to generate an error flag signal and the tolerance reset signal when the tolerance control signal and the window control signal are inputted a predetermined number of times;
- an error check signal generation circuit configured to control an output of the error detection signal.
5 more elements
Dependencies are inferred from the claim text.