Smart erase verify test to detect slow-erasing blocks of memory cells
AssigneeWestern Digital Technologies, Inc.
InventorsLiang Li, Ming Wang
Life of this patent
Estimating the term…
Loading patent…
AssigneeWestern Digital Technologies, Inc.
InventorsLiang Li, Ming Wang
Estimating the term…
Apparatuses and techniques are described for determining if a block of memory cells is slow-erasing during an erase operation for the block. An erase operation performs an additional verify test in a specified erase-verify iteration to check the position of the upper tail of the threshold voltage distribution of the memory cells of a block. If the upper tail is too high, this indicates a slow-erasing block, even if the erase operation is successfully completed within an allowable number of erase-verify iterations. The additional verify test can be initiated using a prefix command which is transmitted with an erase command to the memory chip. Or, it can be initiated by a device parameter on the memory chip.
An apparatus, comprising:
A method, comprising:
An apparatus, comprising:
Dependencies are inferred from the claim text.