Systems and methods of implementing a calibration wordline to compensate for voltage threshold shift in NAND flash memory

A system, comprising:

• at least one memory block comprising multiple memory pages that each comprise a different group of memory cells, each of the memory cells storing an electron charge having a voltage corresponding to a stored data value;
• and
• at least one programmable integrated circuit coupled to multiple separate wordlines, each of the separate wordlines being coupled to a different group of memory cells that corresponds to one of the memory pages of the at least one memory block;
• where a designated one of the multiple memory pages comprises a group of memory cells that are programmed with stored data values corresponding to a pre-defined data pattern;
• and
• where the at least one programmable integrated circuit is programmed to:
• read a current data pattern stored in the memory cells of the designated memory page using a default read compare voltage (Vr);
• then compare the read current data pattern to the pre-defined data pattern to determine a magnitude of a shift in voltage of the stored charge in each of the memory cells of the designated memory page between the current data pattern and the pre-defined data pattern;
• and
• then determine an adjusted read compare voltage (Vr−1) based on the determined magnitude of the shift in voltage of the stored charge in the memory cells of the designated memory page.

An information handling system, comprising:

• a host programmable integrated circuit;
• a solid state drive (SSD) coupled to the host programmable integrated circuit, the SSD comprising:
• at least one memory block comprising multiple memory pages that each comprise a different group of memory cells, each of the memory cells storing an electron charge having a voltage corresponding to a stored data value, and
• at least one programmable integrated circuit coupled to multiple separate wordlines, each of the separate wordlines being coupled to a different group of memory cells that corresponds to one of the memory pages of the at least one memory block,
• where a designated one of the multiple memory pages comprises a group of memory cells that are programmed with stored data values corresponding to a pre-defined data pattern;
• and
• where the at least one programmable integrated circuit of the SSD is programmed to:
• read a current data pattern stored in the memory cells of the designated memory page using a default read compare voltage (Vr),
• then compare the read current data pattern to the pre-defined data pattern to determine a magnitude of a shift in voltage of the stored charge in each of the memory cells of the designated memory page between the current data pattern and the pre-defined data pattern,
• then determine an adjusted read compare voltage (Vr−1) based on the determined magnitude of the shift in voltage of the stored charge in the memory cells of the designated memory page,
• then re-read the stored data value of each given memory cell of the array of memory cells by determining the voltage of the stored charge in the given memory cell relative to the adjusted read compare voltage (Vr−1), and
• then provide the re-read data to the host programmable integrated circuit.