US 11,309,034 B2Granted

Memory cell arrangement and methods thereof

AssigneeFerroelectric Memory GmbH

InventorsMenno Mennenga, Johannes Ocker

Life of this patent

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Abstract

A memory cell arrangement is provided that may include: a plurality of first control lines; a plurality of second control lines; a plurality of third control lines; each of a plurality of memory cell sets includes memory cells and is assigned to a corresponding one of the plurality of first control lines and includes at least a first memory cell subset addressable via the corresponding first control line, a corresponding one of the plurality of second control lines, and the plurality of third control lines, and at least a second memory cell subset addressable via the corresponding first control line, the plurality of second control lines, and a corresponding one of the plurality of third control lines. The corresponding one of the plurality of third control lines addresses the second memory cell subset of each memory cell set of the plurality of memory cell sets.

Claims17

Dependent claims

Memory cell arrangement, comprising:

a first memory cell, a second memory cell, a third memory cell, a fourth memory cell, a fifth memory cell, a sixth memory cell, a seventh memory cell, and an eighth memory cell;
a first bitline assigned to the first memory cell, the second memory cell, the third memory cell, and the fourth memory cell;
a second bitline assigned to the fifth memory cell, the sixth memory cell, the seventh memory cell, and the eighth memory cell;
a first wordline assigned to the first memory cell, the second memory cell, the fifth memory cell, and the sixth memory cell;
a second wordline assigned to the third memory cell, the fourth memory cell, the seventh memory cell, and the eighth memory cell;
a first plateline assigned to the first memory cell, the third memory cell, the fifth memory cell, and the seventh memory cell;
a second plateline assigned to the second memory cell, the fourth memory cell, the sixth memory cell, and the eighth memory cell.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/929,685Filed 15 Jul 2020
Published: US 2021/0090662 A125 Mar 2021
Granted: 19 Apr 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

G11C 11/2253
Auxiliary circuits: address circuits or decoders
G11C 16/24
Auxiliary circuits, e.g. for writing into memory: bit-line control circuits
G11C 11/221
Using ferroelectric elements: using ferroelectric capacitors
G11C 11/2255
Address circuits or decoders: bit-line or column circuits

Family

US 2021/0090662 A1Pre-grant publication · published 25 Mar 2021
US 11,309,034 B2This patent

From the US filing history. Foreign family members aren’t listed.

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