Word line discharge skip for faster read time

A method, comprising:

• performing a first read operation to read data from a first set of memory cell transistors while a first word line connected to the first set of memory cell transistors is biased to a selected word line voltage and a second word line connected to a second set of memory cell transistors is biased to an unselected word line voltage, the unselected word line voltage is greater than the selected word line voltage;
• acquiring a second instruction to perform a second read operation to read data from the second set of memory cell transistors subsequent to performing the first read operation;
• detecting that the second instruction was received prior to discharge of the first word line from the selected word line voltage to the unselected word line voltage;
• determining a partial discharge time delay based on the selected word line voltage;
• detecting that the partial discharge time delay has passed since the first word line began a transition to the unselected word line voltage from the selected word line voltage;
• and
• performing a second read operation to read data from the second set of memory cell transistors while the first word line is biased to the unselected word line voltage and the second word line is biased to the selected word line voltage subsequent to detecting that the partial discharge time delay has passed.

An apparatus, comprising:

• one or more control circuits configured to be in communication with a first word line connected to a first set of memory cell transistors and a second word line connected to a second set of memory cell transistors, the one or more control circuits are configured to set the first word line to a selected word line voltage during a first read operation to read data from the first set of memory cell transistors and set the second word line to an unselected word line voltage during the first read operation, the one or more control circuits are configured to acquire a second instruction to perform a second read operation to read data from the second set of memory cell transistors and detect that the second instruction was received prior to discharge of the first word line from the selected word line voltage to the unselected word line voltage, the one or more control circuits are configured to determine a partial discharge time delay based on a voltage difference between the selected word line voltage and the unselected word line voltage, the one or more control circuits are configured to detect that the partial discharge time delay has passed since the first word line began a transition to the unselected word line voltage from the selected word line voltage and set the second word line to the selected word line voltage during the second read operation to read data from the second set of memory cell transistors subsequent to detection that the partial discharge time delay has passed.