Semiconductor memory device

A semiconductor memory device comprising:

• a plurality of memory blocks;
• and
• a pass transistor (TR) unit configured to transmit a plurality of driving signals to any one memory block, selected among the plurality of memory blocks, in response to a block selection signal and comprising a plurality of pass transistors,
• wherein the pass TR unit comprises:
• a first pass transistor configured to transmit a first driving signal with a first level voltage among the plurality of driving signals and formed in a first active region;
• a second pass transistor configured to transmit a second driving signal with a second level voltage that is higher than the first level voltage, among the plurality of driving signals, and formed in a second active region;
• and
• a third pass transistor configured to transmit a third driving signal with a third level voltage that is higher than the second level voltage, among the plurality of driving signals, and formed in a third active region,
• wherein an area of the third active region is the largest and an area of the first active region is the smallest,
• wherein each of the plurality of memory blocks includes a cell string in which one or more source selection transistors, a first dummy transistor, a plurality of memory cell transistors, a second dummy transistor, one or more third dummy transistors, the one or more third dummy transistors being positioned between the plurality of memory cell transistors, and one or more drain selection transistors which are sequentially coupled in series vertically from a surface of a substrate, and
• wherein, in the pass TR unit:
• a plurality of the first pass transistors transmit, to the one or more source selection transistors and the one or more drain selection transistors, a first driving signal with a first level voltage, among the plurality of driving signals, in response to the block selection signal,
• a plurality of the second pass transistors transmit, to the first to third dummy transistors, a second driving signal with a second level voltage that is higher than the first level voltage, among the plurality of driving signals, in response to the block selection signal, and
• a plurality of the third pass transistors transmit, to the plurality of memory cell transistors, a third driving signal with a third level voltage that is higher than the second level voltage, among the plurality of driving signals, in response to the block selection signal.