Semiconductor circuit and semiconductor circuit system to suppress disturbance in the semiconductor circuit

A semiconductor circuit system, comprising:

• a memory section;
• and
• a controller configured to control a power supply to the memory section, wherein
• the memory section includes:
• a first circuit configured to:
• generate a first inverted voltage of a first voltage at a first node;
• and
• apply the first inverted voltage to a second node;
• a second circuit configured to:
• generate a second inverted voltage of a second voltage at the second node;
• and
• apply the second inverted voltage to the first node;
• a first transistor configured to couple the first node to a third node by turn on of the first transistor;
• a first memory element that includes a pinned layer and a free layer, wherein
• a first terminal of the first memory element corresponds to the pinned layer,
• the pinned layer includes a first ferromagnetic material having a magnetization direction fixed to a specific direction,
• the free layer includes a second ferromagnetic material having a changeable magnetization direction,
• the pinned layer of the first memory element has a first end and a second end opposite to the first end,
• the first end of the pinned layer is coupled to a source of the first transistor,
• the second end of the pinned layer is electrically connected to the free layer, and
• a control voltage is applied to a second terminal of the first memory element, and
• the first memory element is in one of a first resistance state or a second resistance state;
• a second transistor, wherein
• a third voltage is applied to a source of the second transistor,
• a drain of the second transistor is coupled to the third node,
• a gate of the second transistor is coupled to a first specific node, and
• the first specific node is one of the first node or the second node;
• a third transistor, wherein
• a fourth voltage is applied to a source of the third transistor,
• a drain of the third transistor is coupled to the third node,
• a gate of the third transistor is coupled to a second specific node, and
• the second specific node is other of the one of the first node or the second node;
• and
• a driver configured to control an operation of the first transistor and set the control voltage.

A semiconductor circuit, comprising:

• a first circuit configured to:
• generate a first inverted voltage of a first voltage at a first node;
• and
• apply the first inverted voltage to a second node;
• a second circuit configured to:
• generate a second inverted voltage of a second voltage at the second node;
• and
• apply the second inverted voltage to the first node;
• a first transistor configured to couple the first node to a third node by turn on of the first transistor;
• a first memory element, wherein
• a first terminal of the first memory element is coupled to the third node,
• a control voltage is applied to a second terminal of the first memory element, and
• the first memory element is in one of a first resistance state or a second resistance state;
• a second transistor, wherein
• a third voltage is applied to a source of the second transistor,
• a drain of the second transistor is coupled to the third node,
• a gate of the second transistor is coupled to a first specific node, and
• the first specific node is one of the first node or the second node;
• a third transistor, wherein
• a fourth voltage is applied to a source of the third transistor,
• a drain of the third transistor is coupled to the third node,
• a gate of the third transistor is coupled to a second specific node, and
• the second specific node is other of the first node or the second node;
• a fourth transistor, wherein
• the third voltage is applied to a source of the fourth transistor, and
• a drain of the fourth transistor is coupled to the source of the second transistor;
• a fifth transistor, wherein
• the fourth voltage is applied to a source of the fifth transistor, and
• a drain of the fifth transistor is coupled to the source of the third transistor;
• a driver, wherein
• in a first period, the driver is configured to:
• turn off the first transistor and the fifth transistor;
• turn on the fourth transistor;
• and
• set the control voltage to a fifth voltage, and
• in a second period after the first period, the driver is further configured to:
• turn on the first transistor;
• and
• turn off the fourth transistor and the fifth transistor;
• and
• a controller configured to:
• control a power supply to the first circuit and the second circuit;
• and
• stop the power supply to the first circuit and the second circuit in a third period between the first period and the second period.