Memory cell programming that cancels threshold voltage drift

A method of operating memory, comprising:

• programming a memory cell to one of two possible data states by:
• applying a first voltage pulse to the memory cell, wherein the first voltage pulse has a first polarity and a first magnitude;
• applying a second voltage pulse to the memory cell, wherein:
• the second voltage pulse has a second polarity that is opposite the first polarity and is a polarity direction of the one of the two possible data states to which the memory cell is being programmed;
• and
• the second voltage pulse has a second magnitude;
• and
• applying a current pulse to the memory cell while the second voltage pulse is being applied to the memory cell.

An apparatus, comprising:

• a memory having a plurality of memory cells;
• and
• circuitry configured to program a memory cell of the plurality of memory cells to one of two possible data states by:
• applying a first voltage pulse to the memory cell, wherein the first voltage pulse has a positive polarity and a first magnitude, wherein the first magnitude is a same magnitude as a voltage used to distinguish memory cells of the plurality of memory cells programmed to the one of the two possible data states from memory cells of the plurality of memory cells programmed to the other one of the two possible data states;
• and
• applying a second voltage pulse to the memory cell, wherein the second voltage pulse has a negative polarity and a second magnitude.

A method of operating memory, comprising:

• programming a self-selecting memory cell to one of two possible data states by applying a voltage pulse to the self-selecting memory cell, wherein:
• the voltage pulse has a positive polarity and a magnitude that is less than a magnitude of a voltage used to distinguish self-selecting memory cells of the memory programmed to the one of the two possible data states from self-selecting memory cells of the memory programmed to the other one of the two possible data states;
• and
• the method comprises programming the self-selecting memory cell without determining whether the self-selecting memory cell snaps back in response to the applied voltage pulse.

An apparatus, comprising:

• a memory having a plurality of memory cells;
• and
• circuitry configured to program a memory cell of the plurality of memory cells to one of two possible data states by:
• applying a first voltage pulse to the memory cell, wherein the first voltage pulse has a negative polarity and a first magnitude;
• and
• applying a second voltage pulse to the memory cell, wherein the second voltage pulse has a positive polarity and a second magnitude;
• wherein:
• the memory includes a plurality of access lines coupled to the plurality of memory cells;
• the memory cell being programmed is coupled to one of the plurality of access lines;
• and
• the circuitry is configured to program the memory cell to the one of the two possible data states without applying a voltage to the plurality of access lines to which the memory cell being programmed is not coupled.