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US 11,309,018 B2Granted
Stable memory cell identification for hardware security
AssigneeRegents of the University of Minnesota
InventorsMuqing Liu, Chen Zhou, Keshab K. Parhi, Hyung-Il Kim
Life of this patent
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Abstract
A method includes setting an output of each memory cell in an array of memory cells to a same first value, decreasing power to the array of memory cells and then increasing power to the array of memory cells. Memory cells in the array of memory cells with outputs that switched to a second value different from the first value are then identified in response to decreasing and then increasing the power. A set of memory cells is then selected from the identified memory cells to use in hardware security.
Claims15
A method comprising:
- setting an output of each memory cell in an array of memory cells to a same first value;
- decreasing power to the array of memory cells;
- waiting a period of time;
- increasing power to the array of memory cells;
- examining the outputs of the memory cells and identifying as being eligible to be used to provide consistent outputs in hardware security, all memory cells in the array of memory cells whose outputs switched to a second value different from the first value in response to decreasing and then increasing the power;
- selecting from the identified memory cells, a set of memory cells to use in hardware security;
- wherein the period of time is set through steps comprising:
- selecting a proposed time period;
- writing a first value to all memory cells of a test set of memory cells;
- reducing power to the test set of memory cells for the proposed time period and then restoring power to the test set of memory cells;
- reading all of the memory cells in the test set of memory cells;
- identifying which memory cells switched to contain a second value different than the first value;
- counting the identified memory cells that switched to contain the second value;
- writing the second value to all of the memory cells in the test set of memory cells;
- reducing power to the test set of memory cells for the proposed time period and then restoring power to the test set of memory cells;
- reading all of the memory cells in the test set of memory cells;
- identifying which memory cells switched to contain the first value;
- counting the identified memory cells that switched to contain the first value,
- summing the count of the identified memory cells that switched to contain the second value and the count of the identified memory cells that switched to contain the first value to produce a total count for the proposed time period;
- and
- determining that the total count for the proposed time period exceeds a desired number of memory cells and in response setting the proposed time period as the period of time.
18 more elements
A system comprising:
- a memory comprising a plurality of memory cells;
- a memory controller coupled to the memory;
- a power controller coupled to the memory and controlling an amount of power provided to the memory;
- and
- a test controller coupled to the memory controller and the power controller, the test controller applying tests to memory cells of the memory through the memory controller and the power controller to identify a time period, during which no power is provided to the memory, needed to change an output state of a desired number of memory cells in the memory while retaining data remanence in other memory cells;
- wherein the controller applies tests to the memory through steps comprising:
- selecting a time period;
- instructing the memory controller to write a first value to all memory cells of a set of memory cells in the memory;
- instructing the power controller to reduce power to the set of memory cells for the selected time period and then restore power to the set of memory cells;
- instructing the memory controller to read all of the memory cells in the set of memory cells;
- identifying which memory cells switched to contain a second value different than the first value;
- counting the identified memory cells that switched to contain the second value;
- instructing the memory controller to write the second value to all of the memory cells in the set of memory cells;
- instructing the power controller to reduce power to the set of memory cells for the selected time period and then restore power to the set of memory cells;
- instructing the memory controller to read all of the memory cells in the set of memory cells;
- identifying which memory cells switched to contain the first value;
- counting the identified memory cells that switched to contain the first value,
- summing the count of the identified memory cells that switched to contain the second value and the count of the identified memory cells that switched to contain the first value to produce a total count for the time period;
- and
- comparing the total count for the time period to the desired number of memory cells.
17 more elements
A method of identifying stable memory cells comprising:
- reducing power to a set of memory cells for a time period and then increasing power to the set of memory cells, wherein the time period limits how many memory cells have different output values after the power is increased compared to before the power is reduced by retaining data remanence in at least one memory cell;
- storing the addresses of all memory cells that had different output values after the power is increased compared to before the power is reduced as stable memory cells;
- and
- selecting the stable memory cells to use in a hardware security task;
- wherein the time period is set through steps comprising:
- selecting a proposed time period;
- writing a first value to all memory cells of a test set of memory cells;
- reducing power to the test set of memory cells for the proposed time period and then restoring power to the test set of memory cells;
- reading all of the memory cells in the test set of memory cells;
- identifying which memory cells switched to contain a second value different than the first value;
- counting the identified memory cells that switched to contain the second value;
- writing the second value to all of the memory cells in the test set of memory cells;
- reducing power to the test set of memory cells for the proposed time period and then restoring power to the test set of memory cells;
- reading all of the memory cells in the test set of memory cells;
- identifying which memory cells switched to contain the first value;
- counting the identified memory cells that switched to contain the first value,
- summing the count of the identified memory cells that switched to contain the second value and the count of the identified memory cells that switched to contain the first value to produce a total count for the proposed time period;
- and
- determining that the total count for the proposed time period exceeds a desired number of memory cells and in response setting the proposed time period as the time period.
16 more elements
Dependencies are inferred from the claim text.