Variable-latency device to reduce sense error in multi-level multi-bit sensing scheme

A variable-latency computing device comprising:

• a computing module;
• a plurality of enabling units divided into at least two groups;
• a storage operation unit comprising memory cells, word lines arranged in parallel, and bit lines arranged in parallel, wherein the word lines are respectively coupled to the plurality of enabling units, each of the word lines is coupled to the bit lines through the memory cells, the storage operation unit is coupled to the computing module, the memory cells are configured to respectively store data values, the plurality of enabling units are configured to enable the word line, and the storage operation unit is configured to accumulate the data values corresponding to the bit lines and the enabled word line, thereby computing first accumulation values that respectively correspond to the bit lines;
• and
• a detecting controller coupled to the storage operation unit, the computing module, and the plurality of enabling units, wherein the detecting controller is configured to receive the first accumulation values, the detecting controller controls the computing module to stop receiving the first accumulation values when a sum of the first accumulation values is higher than a threshold value, and the detecting controller takes turns to turn off the at least two groups after the computing module stops receiving the first accumulation values;
• wherein when each of the at least two groups enables the word line, the storage operation unit accumulates the data values corresponding to the bit lines and the word line that is enabled by each of the at least two groups, thereby computing second accumulation values that respectively correspond to the bit lines, and the computing module receives and computes the second accumulation values corresponding to the at least two groups, so as to generate a computation value.