Floating body DRAM with reduced access energy

A method of operation in an integrated circuit (IC) memory controller, the method comprising:

• transmitting read transaction component signals for accessing a first group of floating body dynamic random access memory (FBDRAM) storage cells, the read transaction component signals including an activate command and a read command;
• conditionally generating a writeback command with conditional writeback circuitry, the conditional writeback circuitry generating the writeback command in response to one of a predetermined probability, a threshold count of a number of accesses to the first group of the storage cells, or a tag value exhibiting a first sense characteristic;
• and
• performing a writeback operation of sensed data associated with the read command in response to the writeback command.

A memory comprising:

• a memory device including storage cells, each storage cell formed with a metal-oxide-semiconductor (MOS) transistor having a floating body, wherein data is stored as charge in the floating body;
• memory control circuitry to issue a read command to the memory device, the memory control circuitry including a transfer interface to receive a read command to access first data stored in a first group of the storage cells;
• and
• wherein the transfer interface conditionally performs a writeback operation associated with the read command in response to a writeback command generated by conditional writeback circuitry disposed in the memory control circuitry, the conditional writeback circuitry generating the writeback command in response to one of a predetermined probability, a threshold count of a number of accesses to the first group of the storage cells, or a tag value exhibiting a sense characteristic.