Memory device for reducing resources used for training

A memory device comprising:

• a first pin group including a first data pin configured to transmit or receive a first data signal and a first control pin configured to transmit or receive a first control signal;
• a second pin group including a second data pin configured to transmit or receive a second data signal and a second control pin configured to transmit or receive a second control signal;
• a third control pin configured to receive a write data strobe signal;
• first power pins configured to receive a first power voltage, the first power pins being located in a first power area positioned in each of a first region in which the first pin group is located and a second region in which the second pin group is located;
• second power pins configured to receive a second power voltage different from the first power voltage, the second power pins being located in a second power area positioned between the first region and the second region;
• ground pins configured to receive a ground voltage, the ground pins being located in the second power area;
• and
• a write data strobe tree circuitry configured to transmit a first internal write data strobe signal with a first toggle timing to a first circuit block corresponding to the first pin group and to transmit a second internal write data strobe signal with a second toggle timing to a second circuit block corresponding to the second pin group, based on the write data strobe signal,
• wherein the first toggle timing is different from the second toggle timing.

A memory device comprising:

• a write data strobe pin configured to receive a write data strobe signal;
• a first pin group configured to receive first data signals sampled based on the write data strobe signal;
• and
• a second pin group configured to receive second data signals sampled based on the write data strobe signal,
• wherein a first training value of the first pin group is determined based on training a first pin of the first pin group, and
• a second training value of the second pin group of pins is determined based on training a second pin of the second pin group.