Apparatuses and methods for staggered timing of targeted refresh operations

An apparatus comprising:

• a first memory bank including a first plurality of word lines;
• a second memory bank including a second plurality of word lines;
• a first refresh control circuit associated with the first memory bank, wherein responsive to a refresh signal, the first refresh control circuit is configured to provide a first type of refresh address associated with a first number of wordlines as part of a first type of refresh operation;
• a second refresh control circuit associated with the second memory bank wherein responsive to the refresh signal, the second refresh control circuit is configured to provide a second type of refresh address associated with a second number of word lines as part of a second type of refresh operation, wherein the first type of refresh operation draws less power than the second type of refresh operation.