Gain cell embedded DRAM in fully depleted silicon-on-insulator technology

A method of storing data in a gain cell, said gain cell comprising:

• a write bit line terminal connected to a write bit line (WBL);
• a read bit line terminal connected to a read bit line (RBL);
• a write trigger terminal connected to a write word line (WWL) and adapted to input a write trigger signal;
• a read trigger terminal put connected to a read word line (RWL) and adapted to input a read trigger signal;
• at least one body voltage terminal connected to a respective body voltage;
• and
• a plurality of fully depleted silicon-on-insulator (FD-SOI) transistors interconnected to form a storage node for retaining a data signal and comprising at least one write transistor having a gate connected to said write trigger terminal and at least one read transistor having a gate connected to said storage node, at least two of said transistors having respective bodies coupled in a first single well to a first body voltage terminal,
• said method comprising:
• writing data to said gain cell, when a write operation is triggered by said write trigger signal, by connecting said write bit line terminal and said storage node via said at least one write transistor using said write trigger signal;
• and
• reading data from said gain cell, when a read operation is triggered by said read trigger signal, by connecting and disconnecting said read bit line terminal and a diffusion connection of one of said read transistors based on a voltage level at said storage node.

A body-biased sense inverter comprising:

• an input terminal;
• a data output terminal;
• a first FD-SOI PMOS transistor having a first diffusion connection, a gate connection, a second diffusion connection and a bulk connection;
• a first FD-SOI NMOS transistor having a first diffusion connection, a gate connection, a second diffusion connection and a bulk connection;
• and
• a non-biased sense inverter comprising:
• a third FD-SOI PMOS transistor having a first diffusion connection, a gate connection, a second diffusion connection and a bulk connection;
• and
• a third FD-SOI NMOS transistor having a first diffusion connection, a gate connection, a second diffusion connection and a bulk connection, wherein said bulk connection of said third PMOS transistor and said first diffusion connection of said third PMOS transistor are connected to a high supply voltage, said gate connections of said third PMOS transistor and said third NMOS transistor are connected to said data input terminal, and said bulk connection of said third NMOS transistor and said second diffusion connection of said third NMOS transistor are connected to a low supply voltage;
• and
• a comparator having an error detection output terminal, a first input connected to said data output terminal and a second input connected to said second diffusion connection of said third PMOS transistor and said first diffusion connection of said third NMOS transistor, adapted to output an error signal at said error detection output terminal when respective signals at said first input and at said second input are different,
• wherein at least one of said bulk connections is connected to a respective body voltage, said gate connections of said first PMOS transistor and said first NMOS transistor are connected to said data input terminal, and said second diffusion connection of said first PMOS transistor and said first diffusion connection of said first NMOS transistor are connected to said data output terminal.