Delay locked loop circuit and semiconductor memory device having the same

A delay locked loop circuit comprising:

• a divider circuit configured to divide an input clock signal to generate a first divided clock signal, to generate a second divided clock signal having an inverted phase of the first divided clock signal, to generate a third divided clock signal having 90-degree phase difference with the first divided clock signal, and to generate a fourth divided clock signal having an inverted phase of the third divided clock signal;
• a first selector circuit configured to generate the first divided clock signal as a first reference clock signal in response to a first selection signal, and to generate the second divided clock signal as the first reference clock signal in response to a second selection signal;
• a second selector circuit configured to generate the third divided clock signal as a second reference clock signal in response to the first selection signal, and to generate the fourth divided clock signal as the second reference clock signal in response to the second selection signal;
• a first delay circuit configured to delay the first reference clock signal by a first time according to a code value to generate a first clock signal;
• a second delay circuit configured to delay the first divided clock signal by the first time according to the code value to generate a second clock signal;
• a third delay circuit configured to delay the second reference clock signal by the first time according to the code value to generate a third clock signal;
• a clock signal delay path circuit configured to delay the first clock signal and the third clock signal by a second time to generate an output clock signal;
• a clock signal delay replica circuit configured to delay the second clock signal by the second time to generate a feedback clock signal;
• a selection signal generator circuit configured to activate the first selection signal in response to a first edge of the feedback clock signal being present within a first period including a third time before and after the first edge of the first divided clock signal, and to activate the second selection signal in response to the first edge of the feedback clock signal being present within a second period including the third time before and after a second edge of the first divided clock signal;
• a first phase detector circuit configured to detect a phase difference between the first divided clock signal and the feedback clock signal to generate a first phase difference detection signal in response to the first selection signal being activated;
• a second phase detector circuit configured to detect a phase difference between the second divided clock signal and the feedback clock signal to generate a second phase difference detection signal in response to the second selection signal being activated;
• and
• a delay control circuit configured to change the code value in response the first phase difference detection signal or the second phase difference detection signal.

A semiconductor memory device comprising:

• a clock signal input buffer circuit configured to buffer and delay an external clock signal by a fourth time to generate an input clock signal;
• a delay locked loop circuit configured to (a) generate a first clock signal by delaying a first internally generated clock signal obtained by dividing or splitting the input clock signal by a first time according to a code value, in response to a first selection signal, and by delaying a second internally generated clock signal obtained by dividing or splitting the input clock signal by the first time according to the code value, in response to a second selection signal, (b) generate a data strobe signal by delaying the first internally generated clock signal by a second time, (c) generate a second clock signal by delaying the first internally generated clock signal by the first time according to the code value, and (d) generate a feedback clock signal locked to the first internally generated clock signal by delaying the second clock signal by an amount corresponding to the fourth time+the second time;
• a row decoder circuit configured to decode a row address to generate a plurality of word line selection signals;
• a column decoder circuit configured to decode a column address to generate a plurality of column selection signals;
• a memory cell array including a plurality of memory cells, and configured to output data stored in memory cells selected from the plurality of memory cells by the plurality of word line selection signals and the plurality of column selection signals;
• a data read path circuit configured to input the data output from the memory cell array in response to a read command and a latency signal, and to generate the data in response to the first clock signal;
• and
• a data output buffer circuit configured to buffer the data to output buffered data to the outside.