Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle
AssigneeMicron Technology, Inc.
InventorKang-Yong Kim
Life of this patent
Estimating the term…
Abstract
Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.
Claims22
A method, comprising:
- issuing from a controller via a command/address bus, commands to a memory to perform a first duty cycle monitor sequence to determine a first duty cycle result;
- changing with the controller, a duty cycle adjuster code stored in the memory to decrease the duty cycle adjuster code to decrease a high duty cycle based on the first duty cycle result by providing a mode register write command to the memory via the command/address bus;
- issuing from the controller via the command/address bus commands to the memory to perform a second duty cycle monitor sequence to determine a second duty cycle result;
- and
- changing the duty cycle adjuster code stored in the memory to increase the duty cycle adjuster code to increase the high duty cycle based on the second duty cycle result by providing a second mode register write command to the memory via the command/address bus, wherein a magnitude of the increase is different than a magnitude of the decrease.
A method, comprising:
- changing a duty cycle adjuster code stored in a memory by a fast speed to change a duty cycle based on a first duty cycle result of a first duty cycle monitor sequence;
- and
- changing the duty cycle adjuster code stored in the memory by a slow speed to change the duty cycle based on a second duty cycle result of a second duty cycle monitor sequence,
- wherein changing the duty cycle adjuster code comprises providing the duty cycle adjuster code and a mode register write command to the memory by a controller via a command/address bus.
An apparatus, comprising:
- a memory;
- a memory controller coupled to the memory, the memory controller configured to:
- issue commands to the memory to perform a first duty cycle monitor sequence to determine a first duty cycle result;
- change a duty cycle adjuster code of the memory by a first step size to change a duty cycle based on the first duty cycle result;
- issue commands to the memory to perform a second duty cycle monitor sequence to determine a second duty cycle result;
- and
- change the duty cycle adjuster code of the memory by a second step size to change a duty cycle based on the second duty cycle result, wherein the second step size is different than the first step size;
- a command/address bus;
- a data bus;
- and
- a clock bus, wherein the memory controller is coupled to the memory through the command/address bus, the data bus, and the clock bus.
Dependencies are inferred from the claim text.